Microcomputer Monitor Memory for Non-Interruptive Debugging
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Solution Overview
Problem
Conventional microcomputers equipped with debug support units (DSU) face challenges in monitoring internal memory data at arbitrary addresses without halting CPU operations, as they require temporary bus access rights from the CPU, leading to limitations in data reading at arbitrary timing.
Innovation Solution
A microcomputer design incorporating a monitor memory and a monitor memory control unit that allows concurrent copying of data from internal memory to a monitor memory, enabling data reading from the monitor memory without halting CPU operations, while preventing CPU access during monitoring mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the DSU supplies a memory access request to the CPU and acquires bus access rights from the CPU to monitor internal memory, then the DSU can access internal memory, but the CPU bus access operation must be temporarily halted and an arbitration procedure is necessary, preventing the DSU from easily reading data with arbitrary timing
Solution Approach 1:
The patent creates a duplicate copy of the internal memory (monitor memory) that mirrors the original memory contents. The monitor memory control unit simultaneously writes data from internal memory to monitor memory via the internal bus while the CPU operates normally. The DSU can then read from the monitor memory copy without interfering with CPU access to internal memory, eliminating the need to halt CPU operations for monitoring purposes.
Solution Approach 2:
The monitor memory control unit acts as an intermediary between the internal memory and the DSU. It intercepts write operations from internal memory and simultaneously writes the same data to monitor memory. This intermediary mechanism allows the DSU to access monitoring data through the monitor memory without directly competing with the CPU for internal memory access, thus avoiding arbitration delays and CPU halts.
2Ease of operation
If the DSU accesses internal memory via the internal bus during program execution, then the DSU can monitor memory data, but access to internal memory by the DSU is limited and requires temporary halting of CPU operation
Solution Approach 1:
By creating a monitor memory copy of internal memory, the system provides the DSU with direct access to monitoring data without requiring complex bus arbitration. The DSU reads from monitor memory as if it were a simple memory device, greatly simplifying the access operation compared to implementing bus arbitration protocols to access internal memory during CPU operation.
3Productivity
If the CPU sequentially executes programs and writes data in the RAM, then the program execution is maintained, but the DSU cannot easily read data from internal memory with arbitrary timing without halting CPU operation
Solution Approach 1:
The monitor memory serves as a real-time copy of internal memory that is continuously updated by the monitor memory control unit. This allows the DSU to read monitoring data at any arbitrary timing from the monitor memory copy while the CPU continues to execute programs and write data to internal memory without interruption, maintaining both productivity and measurement precision.
Solution Approach 2:
The monitor memory control unit performs preliminary copying of data from internal memory to monitor memory as data is written. This preliminary action ensures that monitoring data is already available in the monitor memory before the DSU needs to read it, allowing arbitrary timing reads without waiting for CPU operations to complete or bus arbitration to occur.
Data Source
AI summary
A microcomputer comprises: a CPU which sequentially executes a program; an internal memory connected to the above CPU via an internal bus; a debug support unit, which monitors the internal state in response to an externally provided command; a monitor memory, which stores data stored in the internal memory, for being accessed by the debug support unit; and a monitor memory control unit, connected to the internal bus, which at a concurrent copy mode performs a control to concurrently write, to the monitor memory, data which is written to the internal memory in response to access from the internal bus, and at a monitor mode performs a control to read data in the monitor memory in response to access from the debug support unit.