Microcomputer Reset Pin Clock Generator Disable

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Solution Overview

Problem

Conventional microcomputers used in electronic control units for vehicles face challenges in reducing current drain without increasing the number of pins, which can shorten battery life due to the inability to shift from normal operation mode to low power consumption mode without additional dedicated pins.

Innovation Solution

A microcomputer with a reset pin that uses a disabling unit to halt the clock generator when the reset signal is active, allowing the microcomputer to determine if it should enter low power consumption mode based on operating conditions and external signals, thereby reducing current drain without additional pins.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If a dedicated pin is provided for shifting to low power consumption mode, then the microcomputer can reduce current drain, but the number of pins increases and package size grows

Engineering Contradiction:
Improvecurrent drainVSAvoidnumber of pins
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The reset pin is assigned multiple functions: it serves both as a reset signal input and as a trigger for entering low power consumption mode. When the reset signal is held at the inactive level (not causing a reset), it simultaneously activates the disabling unit to halt the clock generator and shift the microcomputer into low power consumption mode, thereby reducing current drain without requiring an additional dedicated pin.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The functions of reset signal input and low power consumption mode control are merged into a single pin. The reset pin's signal line is shared with the low power consumption mode control function through the disabling unit, which responds to the reset signal level to control the clock generator and trigger mode shifting, thus combining multiple control functions into one pin.

Inventive Principle:
Principle #5Merging (Combining)

2Speed

If the microcomputer operates continuously in normal operation mode, then it can respond quickly to control targets, but current drain increases and battery life decreases

Engineering Contradiction:
Improveresponse speedVSAvoidbattery life
Core Design Contradiction:
SpeedVSDuration of action of moving object

Solution Approach 1:

The microcomputer dynamically switches between normal operation mode and low power consumption mode based on operational needs. The disabling unit enables this dynamic transition by halting the clock generator when the reset signal is at inactive level, allowing the system to adapt its operational state to balance response speed requirements against battery life conservation.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The microcomputer alternates between active normal operation periods and inactive low power consumption periods. During low power consumption mode, the clock generator is halted and the system periodically monitors for wake-up conditions, creating a periodic on-off pattern that reduces average current drain while maintaining the ability to quickly resume normal operation when needed.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentEP1870794B1Microcomputer with reset pin and electronic control unit with the same
Publication Date: 2016.06.08 DENSO CORP
  • EP1870794B1 patent drawingFigure 1
  • EP1870794B1 patent drawingFigure 2
  • EP1870794B1 patent drawingFigure 3~4

AI summary

In a microcomputer for executing at least one task in normal operation mode, a reset pin is provided. The microcomputer is configured to be reset upon a reset signal with an active level being inputted to the reset pin. A first clock generator is configured to generate a first clock with a first frequency. The microcomputer operates on the first clock as its operation clock. A disabling unit is electrically connected to the reset pin and configured to, upon the reset signal with the active level being input to the reset pin, disable the first clock generator.