Microcomputer Watchdog Timer External Reset Signal Control
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Solution Overview
Problem
Existing microcomputer systems face inefficiencies in resetting external peripheral devices due to the reliance on hardware and software mechanisms that require complex management and often result in inadequate pulse widths for reliable resets.
Innovation Solution
A microcomputer design that includes a watchdog timer-counter and an external reset-signal generator, allowing for independent control of the pulse width of the external reset signal, which can be set by the CPU or manually, ensuring appropriate durations for resetting external peripheral devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the internal reset signal pulse width is used for external peripheral devices, then the microcomputer can be reset efficiently, but the external peripheral devices cannot be reset reliably due to inadequate pulse width
Solution Approach 1:
The patent segments the reset signal generation into two independent parts: an internal reset signal for the microcomputer and an external reset signal for peripheral devices. The external reset-signal generator creates a separate reset signal with independently controllable pulse width, allowing each reset signal to be optimized for its specific purpose without compromising the other.
Solution Approach 2:
The patent applies local quality by providing different reset signal characteristics to different targets. The internal reset signal has a pulse width suitable for microcomputer reset, while the external reset signal has a longer pulse width specifically tailored for reliable peripheral device reset, ensuring each receives the appropriate signal quality for its requirements.
2Reliability
If hardware and software mechanisms are used to reset external peripheral devices, then the reset function can be achieved, but the system complexity and management burden increase
Solution Approach 1:
The external reset-signal generator is configured to automatically generate external reset signals in response to the internal reset signal without requiring software intervention. This self-service mechanism eliminates the need for complex software supervision and control instructions, reducing system complexity while maintaining reliable reset functionality.
Solution Approach 2:
The patent merges the reset signal generation function into the microcomputer's internal circuitry by integrating the external reset-signal generator within the microcomputer. This consolidation eliminates the need for separate external hardware mechanisms and software management, simplifying the overall system while ensuring reliable reset operation.
3Reliability
If the external reset signal pulse width is extended for reliable peripheral reset, then peripheral devices can be reset properly, but the microcomputer reset efficiency is reduced
Solution Approach 1:
By segmenting the reset signal paths, the patent allows the internal reset signal to maintain its original, shorter pulse width for efficient microcomputer reset, while the external reset signal is independently extended for reliable peripheral device reset. This segmentation eliminates the time loss that would occur if a single extended pulse width were applied to both reset operations.
Solution Approach 2:
The patent applies different pulse width characteristics locally to different reset signals: the internal reset signal retains its optimized pulse width for quick microcomputer recovery, while the external reset signal is locally extended to ensure reliable peripheral device reset, thereby avoiding unnecessary time loss in the microcomputer reset process.
Data Source
AI summary
A microcomputer or microcontroller with a watchdog timer-counter also has an external reset signal generator. When the central processing unit of the microcomputer or microcontroller fails to execute its control program correctly, the watchdog timer-counter generates an internal reset signal for a first interval, resetting the central processing unit, and the external reset signal generator generates an external reset signal for a second interval, different from the first interval. The length of the second interval can be set to match the requirements of external peripheral devices to which the external reset signal is supplied.