Microcontroller Access Control Circuitry for Unauthorized Peripheral Access

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Solution Overview

Problem

Current microcontroller designs face safety concerns due to unauthorized access by masters to peripherals, particularly caused by errant software, despite existing protection mechanisms like user/supervisor level access rights and Memory Protection Units.

Innovation Solution

Implementing an access control circuitry with interrupt controllers and a bus interface that monitors interrupt request signals and priority levels to grant access only when specific conditions are met, including matching master IDs and pending interrupt requests, thereby preventing unexpected and unauthorized accesses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If existing protection mechanisms (user/supervisor access rights, MPU, MMU) are implemented, then basic access control is provided, but safety against errant software and unauthorized access remains insufficient

Engineering Contradiction:
Improvesafety against unauthorized accessVSAvoidaccess control mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary access control circuitry layer between masters and peripherals that mediates all access requests. This circuitry receives access requests from masters, evaluates them against predefined rules (including interrupt priority levels and master ID authentication), and only grants access when conditions are satisfied. This mediator approach strengthens security without requiring complete redesign of existing access mechanisms.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The access control function is segmented into distinct evaluation stages: interrupt priority level comparison, master ID authentication, and access condition verification. Each stage independently evaluates a specific aspect of the access request, making the overall system more manageable and easier to implement while providing comprehensive security coverage.

Inventive Principle:
Principle #1Segmentation

2Reliability

If strict access control is implemented to prevent unauthorized access, then security is improved, but access latency and system performance may deteriorate

Engineering Contradiction:
Improveaccess securityVSAvoidaccess speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

Access control rules, including interrupt priority levels and master ID authentication criteria, are established and configured in advance before system operation begins. This preliminary configuration allows the access control circuitry to perform rapid comparisons during runtime without needing to interpret or evaluate complex decision logic in real-time, thus maintaining high access speeds while ensuring security.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent replaces software-based access control mechanisms with a hardware-based access control circuitry that operates at the bus level. This substitution enables faster, hardware-accelerated access decisions that do not depend on software execution speed, thereby reducing access latency while maintaining strict security enforcement.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS9946669B2Method of and circuitry for controlling access by a master to a peripheral, a method of configuring such circuitry, and associated computer program products
Publication Date: 2018.04.17 NXP USA INC
  • US9946669B2 patent drawing
  • US9946669B2 patent drawing
  • US9946669B2 patent drawing

AI summary

A method of controlling access by a master to a peripheral includes receiving an interrupt priority level from an interrupt controller associated with the peripheral, comparing the interrupt priority level with respective a pre-established interrupt access level to obtain an interrupt level comparison result, establishing whether an access condition is satisfied in dependence on the interrupt level comparison result, and if the access condition is satisfied, granting access. If the access condition is not satisfied, access is denied. Further, a circuitry is described including a master, a peripheral, and an access control circuitry including an interrupt controller associated with the peripheral. The access control circuitry is arranged to perform a method of controlling access by the master to the peripheral.