Microcontroller Asynchronous Mode Power Reduction
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Solution Overview
Problem
Dynamic voltage and frequency scaling (DVFS) loses efficacy at lower technology nodes, such as 65 nm and 40 nm, making it insufficient for reducing power consumption in modern system on chips (SOCs).
Innovation Solution
A microcontroller is configured to selectively operate in synchronous or asynchronous modes, with the system controller generating signals to control components to transition between these modes, reducing switching power consumption by adjusting operating states based on CPU idle status and intended power modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If dynamic voltage and frequency scaling (DVFS) is used to reduce power consumption, then power savings are achieved, but DVFS loses efficacy at lower technology nodes such as 65 nm and 40 nm
Solution Approach 1:
The patent changes the operating mode parameter from synchronous to asynchronous mode to resolve the contradiction. By transitioning to asynchronous mode, the microcontroller eliminates the need for clock synchronization mechanisms, thereby reducing switching power consumption effectively even at lower technology nodes where DVFS becomes ineffective.
2Power
If the microcontroller operates in synchronous mode, then normal operation is maintained, but switching power consumption is high
Solution Approach 1:
The patent implements dynamic mode switching between synchronous and asynchronous operating modes. The system controller dynamically adjusts the operating mode based on power consumption requirements and operational needs, allowing the microcontroller to transition between high-performance synchronous mode and low-power asynchronous mode as appropriate.
Data Source
AI summary
A microcontroller that can be configured to selectively operate in a synchronous mode or an asynchronous mode, and a method of selectively switching the operating mode is described. The microcontroller can include a processor and a system controller. The processor can be configured to operate synchronously in a synchronous operating mode and asynchronously in an asynchronous operating mode. The processor can also be configured to generate a processor idle status signal indicative of the processor operating in a reduced power mode, and generate a programming signal. The system controller can be configured to generate an asynchronous mode signal based on the programming signal and the processor idle status signal, and provide the asynchronous mode signal to the processor to control the processor to selectively operate in the synchronous operating mode and in the asynchronous operating mode.