8-bit Microcontroller Bank Select and Indirect Addressing
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Solution Overview
Problem
8-bit microcontrollers are limited by their architecture, which restricts data memory due to the 16-bit instruction word length, making it difficult to accommodate larger data memory without increasing the instruction word length, especially as more peripherals are added, leading to a need for enhanced microcontrollers that can utilize larger data memory without enlarging the instruction word length.
Innovation Solution
An 8-bit microprocessor architecture with a 16-bit instruction word size and an 8-bit data memory size, utilizing a bank select register to select up to 64 memory banks and indirect addressing registers to access up to 16KB of data memory, with specific move instructions allowing access to the entire data memory space through multiple instruction words, and the addition of hardware multiplier and shadow registers for context saving during exceptions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the instruction word length is increased to accommodate larger data memory addresses, then the data memory capacity can be increased, but the instruction word length must be enlarged
Solution Approach 1:
The patent segments the address field into multiple parts distributed across multiple instruction words. The first instruction word contains the upper address bits, the second instruction word contains the lower address bits, and the third instruction word contains the remaining address bits. This segmentation allows the microcontroller to access larger data memory spaces (up to 64KB) without increasing the length of any single instruction word, thereby resolving the contradiction between data memory capacity and instruction word length.
2Adaptability or versatility
If more peripheral devices are added to enhance functionality, then the adaptability is improved, but the data memory requirement increases beyond the limited address space
Solution Approach 1:
The patent transitions from a single-dimension addressing scheme (12-bit address in one instruction word) to a multi-dimensional addressing scheme where the address is distributed across multiple instruction words. This dimensional change in the addressing mechanism enables the system to access significantly larger data memory spaces (up to 64KB) required by enhanced peripheral devices, without requiring a proportional increase in any single instruction word's address field.
Data Source
Figure 1a
Figure 1b
Figure 2~3
AI summary
An 8-bit microprocessor has a program memory having a 16-bit instruction word size and a data memory having an 8-bit data size. An instruction word has a payload size for an address of up to 12 bits. The microprocessor furthermore has a central processing unit coupled with the program memory and the data memory, a bank select register configured to select one of up to 64 memory banks, and an indirect addressing register operable to address up to 16KB of data memory. The CPU is configured to execute a first move instruction having two instruction words and being configured to only access the lower 4KB of the data memory and a second move instruction having three instruction words and configured to access the entire data memory.