Secure Microcontroller Block Encryption External Memory Coherency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Microcontrollers face challenges in managing and securing large memory requirements, especially when using external memory, which introduces latency and performance issues due to encryption and decryption operations, and requires maintaining data coherency across internal and external memory systems.
Innovation Solution
A secure microcontroller system with a bi-directional data path and block-level encryption, using a crypto engine for secure data transmission and storage, along with user-programmable write policies to balance data integrity and performance, ensuring data coherency between the cache and external memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If external memory is used to increase storage capacity, then memory size requirement is satisfied, but data coherency maintenance becomes problematic and performance is reduced
Solution Approach 1:
The memory system is segmented into internal memory (for frequently accessed data) and external memory (for bulk storage), with a cache subsystem managing the segmentation. This allows the microcontroller to maintain performance for critical operations while utilizing external memory for expanded capacity.
Solution Approach 2:
A cache subsystem is introduced as an intermediary between the microcontroller and external memory. The cache maintains a copy of frequently accessed data, acting as a buffer that reduces the impact of external memory latency and maintains data coherency without requiring constant synchronization.
2Reliability
If block-level encryption is implemented for security, then data protection is improved, but processing time increases due to encryption and decryption operations
Solution Approach 1:
Data is encrypted before being stored in external memory, and the encryption keys are pre-managed within the secure microcontroller environment. This preliminary encryption ensures that data remains protected during storage and transmission without requiring continuous encryption/decryption operations during normal read access.
Solution Approach 2:
The cache subsystem creates a copy of encrypted data blocks, allowing the microcontroller to access decrypted copies from the cache for processing while the original encrypted data remains in external memory. This copying mechanism reduces the frequency of encryption/decryption operations.
3Reliability
If data coherency is maintained between cache and external memory, then data integrity is ensured, but write operations introduce latency and reduce performance
Solution Approach 1:
The write policy is made dynamic and configurable, allowing the system to adapt between write-through mode (for data integrity) and write-back mode (for performance). The microcontroller can select the appropriate mode based on application requirements, balancing coherency maintenance with operational speed.
Solution Approach 2:
Instead of immediately synchronizing every write operation, the system uses periodic or batched write-backs where modified cache entries are written to external memory at appropriate intervals or when performance thresholds are met, reducing the impact of individual write operations on overall system performance.
Data Source
AI summary
A secure microcontroller system comprising an integrated cache sub-system, crypto-engine, buffer sub-system and external memory is described according to various embodiments of the invention. The secure microcontroller incorporates block encryption methods to ensure that content communicated between the integrated microcontroller and external memory is protected and real-time performance of the system is maintained. Additionally, the microcontroller system provides a user-configurable memory write policy in which memory write protocols may be selected to balance data coherency and system performance.