Microcontroller Clock Circuitry for EMI Reduction and Peak Current Optimization
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Solution Overview
Problem
Micro-controller systems face high power consumption and electromagnetic compatibility issues due to synchronized clock signals across all modules, leading to peak current spikes and interference, which are challenging to optimize without altering the pre-determined logic architecture.
Innovation Solution
Implementing programmable and configurable delays in the clock architecture to unbalance internal clocks, allowing for adjustable delay settings through user interfaces or system clock frequency adjustments, thereby optimizing electromagnetic compatibility and reducing peak current peaks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If all modules are clocked by the same clock signal, then synchronization and simplicity are improved, but peak current consumption and electromagnetic interference worsen
Solution Approach 1:
The patent applies dynamics by making the clock signal characteristics variable rather than fixed. Specifically, it introduces adjustable delay elements that can dynamically shift the phase of clock signals delivered to different modules. This dynamic adjustment allows the system to optimize power consumption by staggering the active edges of clock signals across modules, thereby avoiding simultaneous switching of numerous sequential cells and reducing peak current demands while maintaining operational synchronization.
Solution Approach 2:
The patent implements parameter changes by modifying the temporal characteristics of clock signals. It introduces delay parameters (such as delay1, delay2, delay3 for different modules) that can be adjusted to change the phase relationship between clock signals. By changing these delay parameters, the system optimizes the distribution of switching events over time, reducing electromagnetic interference and peak current consumption while preserving the functional synchronization needed for proper operation.
2Device complexity
If all modules are clocked by the same clock signal, then system simplicity is improved, but electromagnetic compatibility worsens
Solution Approach 1:
The patent applies dynamics by making the clock signal characteristics variable rather than fixed. Specifically, it introduces adjustable delay elements that can dynamically shift the phase of clock signals delivered to different modules. This dynamic adjustment allows the system to optimize power consumption by staggering the active edges of clock signals across modules, thereby avoiding simultaneous switching of numerous sequential cells and reducing peak current demands while maintaining operational synchronization.
Solution Approach 2:
The patent implements parameter changes by modifying the temporal characteristics of clock signals. It introduces delay parameters (such as delay1, delay2, delay3 for different modules) that can be adjusted to change the phase relationship between clock signals. By changing these delay parameters, the system optimizes the distribution of switching events over time, reducing electromagnetic interference and peak current consumption while preserving the functional synchronization needed for proper operation.
3Use of energy by moving object
If clock signals are unbalanced with different delays, then peak current and electromagnetic interference are reduced, but system complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the clock distribution system into separate, independently controllable paths for different modules. Instead of a single unified clock signal, the system segments the clock distribution into multiple paths (clock1, clock2, clock3) with independent delay elements. This segmentation allows each module to receive a clock signal with customized delay characteristics, enabling optimization of power consumption and electromagnetic interference for each module while maintaining overall system functionality.
Solution Approach 2:
The patent introduces intermediary delay elements (delay elements 1, 2, 3) that act as mediators between the clock source and the modules. These intermediary components buffer and condition the clock signals, introducing controlled delays to stagger the active edges. By placing these intermediaries in the clock distribution path, the system achieves the desired phase shifting and current optimization without requiring fundamental changes to the module architecture or logic design.
4Object-generated harmful factors
If delay parameters are adjusted for optimization, then electromagnetic compatibility and power consumption are improved, but ease of operation worsens
Solution Approach 1:
The patent implements self-service by enabling the system to automatically optimize its own clock distribution parameters. The delay elements can be configured based on the specific operational requirements and electromagnetic environment, allowing the system to self-adjust without requiring complex external configuration procedures. This self-service capability simplifies operation by making the optimization process transparent to the user while maintaining the benefits of reduced electromagnetic interference and power consumption.
Data Source
AI summary
A system comprises a central processing unit and a set of peripheral units accessible by the CPU and being able to be driven by the same clock source. At least one programmable delay line is located in the clock branch of one of the peripheral units and has a delay selection input that is accessible by software running on the system.