Microcontroller Cluster Parallel Processing for 5G Edge AI

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Solution Overview

Problem

Current computational devices for 5G networks and beyond lack the necessary speed, memory, cost-effectiveness, flexibility, low carbon footprint, and compact size to efficiently support AI algorithms both in data centers and edge computing devices.

Innovation Solution

A parallel computing device comprising a cluster of low-cost, energy-efficient microcontrollers connected via the I2C communication protocol, with a master-slave architecture and no need for an operating system or cooling systems, allowing for scalable and flexible computational capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If mainstream clusters or GPUs are used to speed up computations, then computational speed and processing capability are improved, but power consumption and carbon footprint increase significantly

Engineering Contradiction:
Improvecomputational speedVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent employs low-cost, energy-efficient microcontrollers instead of expensive, high-power GPUs or mainstream cluster nodes. Each microcontroller is designed to perform specific computational tasks efficiently and can be replaced or reconfigured as needed, providing a cost-effective and energy-efficient alternative to traditional high-performance computing hardware.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent changes the operational parameters of the computing system by using microcontrollers operating at lower voltage and power consumption levels compared to GPUs or mainstream cluster nodes. This parameter change enables the system to achieve acceptable computational speed while dramatically reducing power consumption and carbon footprint.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If specialized hardware like GPUs is used for parallel processing, then computational capability is improved, but device complexity and cost increase

Engineering Contradiction:
Improveparallel processing capabilityVSAvoidhardware complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the parallel processing system into multiple independent microcontroller units instead of using a single complex GPU or centralized processing unit. Each microcontroller can operate independently or in coordination with others, providing parallel processing capability while maintaining simplicity in individual device design and reducing overall system complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses universal microcontroller units that can perform multiple functions and be configured for different computational tasks. These microcontrollers serve as both processing units and communication nodes, eliminating the need for specialized hardware components and reducing device complexity while maintaining parallel processing capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If operating systems are installed on computational devices to manage resources, then system management and adaptability are improved, but power consumption and device complexity increase

Engineering Contradiction:
Improvesystem management capabilityVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by stationary object

Solution Approach 1:

The patent extracts and removes the operating system layer from the microcontroller system. Instead of running full operating systems that consume significant power and resources, the system uses a streamlined firmware or bare-metal programming approach that provides essential system management functions with minimal power consumption and device complexity.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent implements self-service mechanisms where microcontrollers autonomously manage their own resources and operations without requiring a full operating system. Each microcontroller can independently handle task scheduling, memory management, and communication protocols, reducing the computational overhead and power consumption associated with traditional operating systems.

Inventive Principle:
Principle #25Self-service

4Productivity

If high-performance computing hardware is deployed to support AI algorithms, then computational resources are improved, but carbon footprint and environmental impact increase

Engineering Contradiction:
ImproveAI processing capabilityVSAvoidcarbon footprint
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent uses low-power microcontrollers that consume minimal energy during operation, thereby reducing the carbon footprint associated with AI processing. These energy-efficient devices can be deployed in large numbers for distributed AI computing without significantly increasing overall environmental impact, unlike high-power GPUs or data center hardware.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent replaces traditional high-power mechanical cooling systems and energy-intensive hardware with solid-state microcontrollers that generate minimal heat. This substitution eliminates the need for complex cooling infrastructure and reduces the indirect carbon footprint associated with manufacturing, operating, and maintaining high-performance computing hardware.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS20250199994A1Parallel processing using a microcontroller based computing apparatus
Publication Date: 2025.06.19 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • US20250199994A1 patent drawing
  • US20250199994A1 patent drawing
  • US20250199994A1 patent drawing

AI summary

The disclosure relates to a computing apparatus, for parallel computing, a method, a system, and a non-transitory computer readable media. The computing apparatus comprises a plurality of microcontrollers, including a master microcontroller and at least two slave microcontrollers. The computing apparatus comprises a bus, operatively interconnecting the plurality of microcontrollers. The computing apparatus comprises an input/output (I/O) interface operatively interconnected to the master microcontroller. The computing apparatus comprises a power supply. The master microcontroller is operative to receive executable fdes through the I/O interface, to distribute the executable fdes to the at least two slave microcontrollers, to receive a response from the at least two slave microcontrollers and to transmit an aggregated response through the I/O interface.