Microcontroller Context Switching with Universal Register Mapping

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Solution Overview

Problem

Existing microcontrollers face bottlenecks in memory access due to limitations in their architecture, particularly in switching between memory banks, which hampers performance.

Innovation Solution

A microprocessor or microcontroller device with a central processing unit (CPU) that includes a data memory divided into multiple banks, with special function registers memory-mapped to all banks, allowing automatic saving and restoration of context during switches, and an interrupt unit for induced context switching, enhancing memory access efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a banking system with separated program and data memories is used, then memory access flexibility is improved, but memory access speed deteriorates due to bank switching requirements

Engineering Contradiction:
Improvememory access flexibilityVSAvoidmemory access speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The data memory is divided into multiple banks (Bank 0, Bank 1, etc.) that can be independently selected and accessed. This segmentation allows parallel access paths and reduces contention when switching between different memory regions, improving overall access speed while maintaining flexibility.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The bank select register and indirect addressing registers are memory-mapped to all memory banks, making them universally accessible regardless of which bank is currently selected. This eliminates the need for complex bank switching sequences and allows direct access to these critical registers from any bank, thereby improving memory access speed.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Ease of operation

If manual bank switching is implemented, then memory access control is improved, but operation complexity deteriorates due to required re-programming of bank select register

Engineering Contradiction:
Improvememory access controlVSAvoidoperation complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The context switching mechanism automatically saves and restores the contents of the bank select register, status register, and indirect addressing registers during interrupt handling. This self-service approach eliminates the need for manual bank switching code and reduces operational complexity while maintaining precise control over memory access.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The bank select register and other critical registers are pre-configured and automatically saved before context switching occurs. This preliminary action ensures that the correct bank is already selected and its state preserved before the interrupt service routine begins, simplifying the overall operation.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If context switching is implemented without automatic saving, then processing capability is improved, but time loss deteriorates due to manual saving and restoring of registers

Engineering Contradiction:
Improveprocessing capabilityVSAvoidcontext switch time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The microcontroller automatically saves the contents of the status register, bank select register, and indirect addressing registers to dedicated storage locations during context switching. This automatic saving and restoring mechanism eliminates manual intervention and reduces context switch time, thereby improving processing capability and reducing time loss.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The context switching functionality is merged with the interrupt handling mechanism, so that saving and restoring of register states is integrated into the standard interrupt response flow. This combination eliminates separate save/restore operations and reduces the overall time required for context switching.

Inventive Principle:
Principle #5Merging (Combining)

4Ease of operation

If special function registers are memory-mapped to all banks, then register accessibility is improved, but memory space utilization deteriorates

Engineering Contradiction:
Improveregister accessibilityVSAvoidmemory space utilization
Core Design Contradiction:
Ease of operationVSQuantity of substance

Solution Approach 1:

The bank select register, status register, and indirect addressing registers are memory-mapped to all memory banks at fixed addresses. This universal mapping allows these critical registers to be accessed from any bank without requiring bank switching, improving accessibility. The trade-off in memory space is acceptable because these are control registers rather than data storage locations.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The memory-mapped registers serve as intermediaries between the CPU and the bank switching mechanism. By providing direct access to these registers through memory-mapped I/O, the system eliminates the need for complex pointer arithmetic and bank switching code, improving ease of operation despite the memory space overhead.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8539210B2Context switching with automatic saving of special function registers memory-mapped to all banks
Publication Date: 2013.09.17 MICROCHIP TECHNOLOGY INC
  • US8539210B2 patent drawing
  • US8539210B2 patent drawing
  • US8539210B2 patent drawing

AI summary

A microcontroller device has a central processing unit (CPU); a data memory coupled with the CPU divided into a plurality of memory banks, a plurality of special function registers and general purpose registers which may be memory-mapped, wherein at least the following special function registers are memory-mapped to all memory banks: a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from the context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.