Microcontroller Logic Cell With CPU-Driven LUT Configuration

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Solution Overview

Problem

Conventional microcontrollers with configurable logic cells have limited flexibility and require complex setup for combinational logic functions, often necessitating multiple peripherals for simple tasks, which can be wasteful and restrictive due to predefined logic elements.

Innovation Solution

A microcontroller with a configurable logic cell formed by a look-up table using a plurality of memory cells, an input multiplexer unit, and a special function input register, allowing direct input signal provision from the central processing unit, enabling selection and buffering of internal and external signals for flexible logic operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional configurable logic cells are used with predefined logic elements, then device complexity is reduced, but adaptability and versatility are limited

Engineering Contradiction:
Improvelogic function flexibilityVSAvoidsetup complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic reconfigurability by allowing the logic cell to be programmed at runtime through a CPU-accessible interface. The logic function is not fixed at fabrication but can be dynamically changed by loading new truth tables into the lookup table memory, enabling the same hardware to adapt to different logic requirements during operation.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the functional parameters of the logic cell by using a lookup table approach where the logic function is defined by programmable data in memory rather than fixed hardware connections. This allows the same physical structure to implement different logic functions by simply changing the stored truth table data, providing flexibility without increasing physical complexity.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If multiple configurable logic cells are allocated for simple bridging needs, then logic function coverage is improved, but resource allocation efficiency deteriorates

Engineering Contradiction:
Improvelogic function coverageVSAvoidperipheral resource usage
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent creates a universal logic cell that can perform multiple different logic functions through a single reconfigurable unit. The lookup table structure allows the same hardware to implement any combinational logic function by loading appropriate truth tables, eliminating the need for multiple dedicated logic cells for different functions and improving resource utilization.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If conventional configurable logic cells are used with limited sequential functionality, then device complexity is minimized, but adaptability for sequential logic operations deteriorates

Engineering Contradiction:
Improvesequential logic capabilityVSAvoidconfiguration complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the logic cell into distinct functional components: a programmable lookup table for combinational logic, separate flip-flop elements for sequential functionality, and control registers for configuration. This segmentation allows independent optimization of each component and enables flexible combination of combinational and sequential logic without increasing overall complexity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10949204B2Microcontroller with configurable logic peripheral
Publication Date: 2021.03.16 MICROCHIP TECHNOLOGY INC
  • US10949204B2 patent drawing
  • US10949204B2 patent drawing
  • US10949204B2 patent drawing

AI summary

A microcontroller has a central processing unit, memory, I/O ports and a plurality of peripheral units, wherein one of the peripheral units is a configurable logic cell. The configurable logic cell is formed by a look-up table formed by a plurality of memory cells receiving a predefined number of input address signals selectable from internal signals provided by the peripheral units and at least one external signal provided by at least one external pin and generating an output signal. The central processing unit is configured to directly provide input address signals for the look-up table.