Microcontroller Dual-Bus Architecture for Parallel Data Access
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Solution Overview
Problem
Traditional microcontroller architectures face performance bottlenecks and delays due to single-bus data transmission, priority arbitration issues, and inefficiencies in data reading and writing processes, which hinder optimal data exchange between components.
Innovation Solution
The proposed microcontroller architecture introduces a dual-bus system with a first bus for direct microcontroller-data memory communication and a second bus for system memory and external device communication, incorporating a cache controller and buffer memory to optimize data access and reduce resource competition, allowing the DMA to access memory independently without bus control transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single bus is used for all data transmission between microcontroller, DMA, memory, and external devices, then the architecture is simple and easy to manufacture, but data transmission efficiency deteriorates due to priority arbitration delays and resource competition
Solution Approach 1:
The single bus is segmented into two separate buses: a first bus connecting the microcontroller to data memory, and a second bus connecting the system memory to external devices. This segmentation eliminates resource competition between the microcontroller and DMA controller, allowing parallel data transmission and improving overall system productivity while maintaining manufacturing simplicity through modular bus design.
2Device complexity
If the microcontroller and DMA share the same bus for data transmission, then the device complexity is low, but the data reading time increases due to bus control transfer requirements
Solution Approach 1:
The bus system is divided into a first bus for microcontroller-data memory communication and a second bus for system memory-external device communication. This allows the microcontroller to access data memory directly through the first bus without requiring bus control transfers, eliminating the time loss associated with arbitration and control switching while maintaining manageable device complexity through structured bus architecture.
3Adaptability or versatility
If the system memory supports multiple master ports for data transmission, then the adaptability of the system is improved, but performance bottlenecks and arbitration delays worsen the overall system speed
Solution Approach 1:
The system memory interface is segmented into two independent access paths: one through the first bus for microcontroller access and another through the second bus for DMA and external device access. This segmentation maintains the adaptability of supporting multiple master ports while eliminating arbitration delays, as each bus operates independently without competing for the same resources, thereby improving data transmission speed.
4Extent of automation
If bus control transfer is required for DMA memory access, then the system maintains centralized control, but the productivity decreases due to control switching overhead
Solution Approach 1:
The bus control is segmented such that the microcontroller has dedicated control over the first bus while the DMA controller has dedicated control over the second bus. This segmentation eliminates the need for control transfer between devices, allowing the DMA to access memory directly without switching overhead, thereby improving productivity while maintaining centralized system control through coordinated bus management.
Data Source
AI summary
An architecture for a microcontroller includes a microcontroller, a system memory, an instruction memory, a data memory, a first bus, and a second bus, where the first and second buses perform functions of a single bus. The microcontroller connects to both buses. The instruction memory and the data memory are connected to the first bus. The system memory is connected to the second bus. The microcontroller transmits and receives data to and from the instruction memory and the data memory through the first bus. The microcontroller transmits and receives data to and from the system memory through the second bus. The instruction memory and the data memory transmit and receive data to and from the system memory through the second bus connected to the first bus, avoiding delays caused by rights and priorities and arbitration of same.