Microcontroller Reference Time Base with Dual-Clock Counter Access

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Solution Overview

Problem

Existing microcontrollers face challenges in maintaining a precise reference time base during standby mode and run mode, leading to reduced reactivity and limited communication throughput due to the limitations of low-frequency and high-frequency hardware clocks.

Innovation Solution

A method is proposed to generate a low-frequency clock signal for standby mode and a high-frequency clock signal for run mode, allowing the reference time base to be updated and accessed with low latency, using a counter register that is clocked with the high-frequency signal in run mode, and synchronized with a root counter register for precise timekeeping.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If a low-frequency clock signal (32 kHz) is used to clock the counter in standby mode, then power consumption is reduced and the counter can operate during standby, but the access speed to the counter becomes slow and system reactivity is reduced

Engineering Contradiction:

Improvepower consumptionVSAvoidaccess speed to counter

Core Design Contradiction:

Use of energy by stationary objectVSSpeed

Solution Approach 1:

The patent divides the counter into two separate counters: a first counter clocked by a low-frequency signal for standby mode operation, and a second counter clocked by a high-frequency signal for run mode operation. This segmentation allows each counter to be optimized for its specific operating mode, resolving the contradiction between low power consumption and fast access speed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent dynamically switches between two different clocking mechanisms based on the operating mode. In standby mode, the low-frequency clock is used to minimize power consumption. In run mode, the high-frequency clock is used to maximize access speed. This dynamic adaptation resolves the contradiction by allowing the system to have both low power consumption and fast access speed at different times.

Inventive Principle:

Principle #15Dynamics

2Speed

If a high-frequency clock signal is used to clock the counter in run mode, then access speed to the counter is fast, but the counter cannot operate during standby mode and the time reference is lost

Engineering Contradiction:

Improveaccess speed to counterVSAvoidoperability in standby mode

Core Design Contradiction:

SpeedVSAdaptability or versatility

Solution Approach 1:

The patent segments the time-keeping function into two separate counters with different clocking mechanisms. The first counter operates during standby mode using a low-frequency clock, while the second counter operates during run mode using a high-frequency clock. This segmentation allows the system to maintain time reference capability in both standby and run modes while providing fast access speed when needed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent creates a universal time-keeping system that can operate in both standby and run modes through the use of two counters. The system universally provides time reference functionality regardless of the operating mode, with the first counter handling standby mode and the second counter handling run mode, thus resolving the contradiction between fast access speed and operability in standby mode.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Use of energy by stationary object

If multiple clock cycles are needed to program interrupts in comparator register at low frequency, then power consumption is lower, but the programming time increases and critical section duration increases

Engineering Contradiction:

Improvepower consumptionVSAvoidprogramming time

Core Design Contradiction:

Use of energy by stationary objectVSLoss of time

Solution Approach 1:

The patent segments the interrupt programming function between two counters operating at different frequencies. The low-frequency counter is used during standby mode where interrupt programming occurs less frequently, minimizing power consumption. The high-frequency counter is used during run mode where fast interrupt programming is critical, reducing programming time. This segmentation resolves the contradiction between low power consumption and short programming time.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent dynamically adapts the clock frequency used for interrupt programming based on the operating mode. In standby mode, the low-frequency clock is used to minimize power consumption during interrupt programming. In run mode, the high-frequency clock is used to minimize programming time and reduce critical section duration. This dynamic adaptation resolves the contradiction by allowing the system to optimize for power consumption or programming time depending on the operational context.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS12081224B2Method for communicating a reference time base in a microcontroller, and corresponding microcontroller integrated circuit

Publication Date: 2024.09.03 STMICROELECTRONICS (GRAND OUEST) SAS

AI summary

In an embodiment a method includes generating a low-frequency clock signal having a first frequency, in a standby mode and in a run mode of the CPU, generating a high-frequency clock signal having a second frequency higher than the first frequency, in the run mode, updating a value of the reference time base at each period of the low-frequency clock signal in the standby mode, and accessing the counter register with the high-frequency clock signal in the run mode.