Microcontroller Error Output Circuit for Low-Power Debugging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices with duplicated circuits, such as microcontrollers, power consumption increases significantly during debugging, leading to excessive part costs and space requirements, especially when all CPU cores operate under high loads.
Innovation Solution
A microcontroller design that includes a first signal processing circuit, a second signal processing circuit, a comparing circuit, a suppressing signal input unit, and a pseudo error signal output circuit, which suppresses the operation of the second signal processing circuit and comparing circuit during debugging, outputting a pseudo error signal instead of a real error signal to reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If all CPU cores operate with high loads during debugging, then debugging functionality is improved, but power consumption increases excessively
Solution Approach 1:
The patent applies dynamics by making the operation of the second CPU core and comparing circuit adjustable rather than static. A suppressing signal input unit receives control signals that dynamically adjust whether the second core operates in comparison mode or is suppressed, allowing the system to adapt its power consumption characteristics based on operational context (debugging vs. normal operation).
Solution Approach 2:
The patent changes the operational parameter of the second CPU core from always-active to conditionally-active based on suppressing signals. By modifying the operational state parameter (operating vs. suppressed) of the second core and comparing circuit, the system achieves variable power consumption levels while maintaining debugging capability when needed.
2Reliability
If the second signal processing circuit and comparing circuit are always operational, then reliability is improved through error detection, but power consumption increases
Solution Approach 1:
The system dynamically adjusts the activation state of the second signal processing circuit and comparing circuit based on operational mode. During normal operation, both circuits are active to provide error detection and improve reliability. During debugging or low-power modes, the suppressing signal deactivates these circuits, reducing power consumption while maintaining the capability to enable them when reliability is needed.
Solution Approach 2:
The patent implements periodic or conditional activation of the error detection circuits rather than continuous operation. The suppressing signal mechanism allows the system to periodically enable or disable the second core and comparing circuit based on whether error detection is currently needed, achieving a balance between reliability and power consumption through intermittent operation.
3Ease of operation
If design is adapted to maximum power consumption during debugging, then debugging capability is maintained, but part cost and space become excessive
Solution Approach 1:
The patent makes the second CPU core and comparing circuit multi-functional by enabling them to serve dual purposes: error detection during normal operation and debugging assistance when activated. The same hardware components perform different functions depending on the suppressing signal state, eliminating the need for separate dedicated debugging hardware and reducing overall part cost and space requirements.
Solution Approach 2:
The system uses dynamic control signals to enable the existing hardware components to adapt their function based on operational mode. The suppressing signal mechanism allows the second core and comparing circuit to be activated for debugging without requiring additional dedicated debugging hardware, thereby avoiding increased part cost and space while maintaining full debugging capability.
Data Source
AI summary
To provide a microcontroller that suppresses increase of power consumption during debugging, a microcontroller according to the present invention includes a first signal processing circuit, a second signal processing circuit that performs signal processing in the same manner as the first signal processing circuit, a comparing circuit that compares a processing result of the first signal processing circuit and a processing result of the second signal processing circuit with each other, and outputs an error signal when an error is detected, a suppressing signal input unit that receives a suppressing signal for suppressing an operation of the second signal processing circuit and an operation of the comparing circuit, a suppressing circuit that receives the suppressing signal from the suppressing signal input unit and suppresses the operation of the second signal processing circuit and the operation of the comparing circuit, and a pseudo error signal output circuit that outputs a pseudo error signal in place of the error signal, when the operation of the second signal processing circuit and the operation of the comparing circuit are suppressed.