Microcontroller Frame Replication With DMA-Based Duplicate Discard
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Solution Overview
Problem
Existing communication protocols for microcontrollers require significant hardware and software resources to handle redundant packet transmission and reception, leading to inefficiencies in managing and discarding duplicate packets.
Innovation Solution
The use of Direct Memory Access (DMA) circuits and frame parser hardware in microcontrollers to efficiently duplicate and discard redundant packets, reducing overhead by offloading CPU tasks and optimizing packet processing through descriptor formats and R-tag comparisons.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional packet processing methods are used in microcontrollers, then packet transmission and reception can be handled, but CPU loading increases and system performance decreases
Solution Approach 1:
The DMA circuit performs packet processing operations autonomously without requiring continuous CPU intervention. The system uses self-service mechanisms where the DMA circuit manages packet duplication and discarding based on R-tag comparisons, freeing the CPU from routine packet handling tasks while maintaining efficient packet processing throughput.
Solution Approach 2:
The patent replaces CPU-based mechanical packet processing with a DMA circuit that handles packet operations independently. This substitution eliminates the bottleneck where CPU must manually manage each packet's transmission and reception, thereby reducing CPU loading while maintaining or improving packet processing efficiency through parallel hardware operations.
2Reliability
If redundant packets are transmitted for reliability, then packet delivery assurance improves, but system overhead increases
Solution Approach 1:
The system implements intelligent packet discarding based on R-tag comparisons. When the DMA circuit receives a packet with an R-tag that matches previously received packets, it automatically discards the redundant packet without processing. This selective discarding mechanism maintains reliability by keeping only unique packets while recovering system resources by eliminating unnecessary processing of duplicate packets, thereby reducing overhead.
Solution Approach 2:
The patent uses R-tags as copies or identifiers that accompany packets to enable rapid recognition of redundant packets. Instead of comparing entire packets which is computationally expensive, the system uses these R-tag copies to quickly identify duplicates, reducing the overhead associated with handling redundant packets while maintaining delivery assurance.
3Ease of operation
If packet processing is handled by CPU, then control flexibility is maintained, but bus access frequency increases
Solution Approach 1:
The DMA circuit operates as a self-service unit that independently manages packet processing operations including reading packets from the bus, comparing R-tags, duplicating packets, and discarding redundant packets. This eliminates the need for the CPU to continuously access the bus for packet handling, thereby reducing bus access frequency and time while maintaining control flexibility through programmed DMA operations and interrupt-based CPU involvement only when necessary.
Data Source
AI summary
Some aspects of the present disclosure relate to a network processor. The network processor includes a system bus, a central processing unit (CPU) coupled to the system bus, a random access memory (RAM) coupled to the CPU via the system bus; a plurality of network ports coupled to the CPU and the RAM; and a network bridge coupled between the CPU and the plurality of network ports. The network bridge includes a first transmit Direct Memory Access (DMA) circuit and a first transmit memory buffer coupled between the first transmit DMA circuit and a first network port, and a receive memory buffer and frame parser hardware arranged between the receive memory buffer and the system bus.