Microcontroller Interface Module for Secure External Memory Storage

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Solution Overview

Problem

Microcontrollers in embedded systems, such as those in vehicles, face limitations in internal working memory capacity and cost, making it difficult to implement error correction in external memory connections, which are often not expandable and lack error correction functions.

Innovation Solution

A method where a shared memory space is reserved for data elements and error correction values during program creation, allowing both to be written in a single addressing phase by an interface module within the microcontroller, eliminating the need for independent address calculations and software modifications.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If external memory is used to expand working memory capacity, then memory capacity is increased, but error correction functionality is lost

Engineering Contradiction:
Improvememory capacityVSAvoiderror correction
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent reserves memory space for error correction values in advance during the linking phase, before the program is executed. This preliminary allocation of space allows the external memory to accommodate both data and error correction information without requiring special hardware support, thus maintaining reliability while using cost-effective external memory expansion

Inventive Principle:
Principle #10Preliminary action

2Reliability

If error correction values are stored separately with independent addressing, then data integrity is maintained, but memory access time increases

Engineering Contradiction:
Improvedata integrityVSAvoidmemory access time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent merges the storage of data elements and their associated error correction values into a single continuous memory block. By combining these normally separate storage operations into one unified structure, the system can retrieve both data and error correction information simultaneously in a single memory access, maintaining data integrity while eliminating the time penalty of separate addressing

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If processor core or software is modified to implement error correction, then error correction functionality is achieved, but device complexity increases

Engineering Contradiction:
Improveerror correctionVSAvoidprocessor modification
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary layer at the linker level that handles error correction value storage automatically. This mediator translates high-level program requirements into low-level memory arrangements with embedded error correction capabilities, allowing error correction functionality to be achieved without modifying the processor core or application software, thus avoiding increased device complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11561857B2Method for the secured storing of a data element to be stored by a computer program in an external memory
Publication Date: 2023.01.24 ROBERT BOSCH GMBH
  • US11561857B2 patent drawing
  • US11561857B2 patent drawing

AI summary

A method for the secured storing of a data element to be stored by a computer program in an external memory, which is connected to a microcontroller, the microcontroller including an interface module, which is configured to calculate error correction values for data elements including, when creating the computer program, during a determination of memory addresses of the computer program, determining a memory address in the external memory for the data element, a shared memory space requirement of data element and associated error correction value being taken into account; and during execution of the computer program, receiving the data element by the interface module; calculating an error correction value for the data element by the interface module; and writing, starting at the memory address, the data element and immediately thereafter the calculated error correction value within one addressing phase by the interface module.