Microcontroller-Mediated Memory Access for Heterogeneous Task Dispatch
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Solution Overview
Problem
Current heterogeneous processor systems face inefficiencies due to fixed system memory allocation for accelerator function units (AFUs), requiring context switches and unbalanced task distribution, which hampers performance and resource utilization.
Innovation Solution
A processing system with a microcontroller-mediated memory access method that dynamically allocates tasks by sharing virtual addresses between the core and AFUs, allowing efficient task dispatch and execution through a memory access unit, and utilizing a round-robin method for scheduling memory access requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the AFU is directly connected to the main bus and system memory, then the AFU can access system memory directly, but the amount of space in system memory available to the AFU is fixed and cannot be dynamically allocated
Solution Approach 1:
The patent introduces a memory access unit as an intermediary component between the AFU and system memory. This unit manages memory access requests and enables dynamic allocation of memory spaces to multiple AFUs, resolving the contradiction between direct access efficiency and allocation flexibility. The memory access unit acts as a mediator that maintains high access efficiency while providing adaptable memory space management.
2Productivity
If tasks are copied from user space to kernel space for execution by AFU, then tasks can be executed by the accelerator, but context switch operations are required which consume too many resources
Solution Approach 1:
The patent merges user space and kernel space memory regions by allowing AFUs to directly access memory spaces allocated through the memory access unit. This eliminates the need for separate user space/kernel space copying operations and associated context switches, thereby reducing resource consumption while maintaining task execution capability.
3Adaptability or versatility
If several AFUs are arranged in one chip to share tasks, then task distribution is enabled, but without coordination the AFU task distribution will be unbalanced and performance cannot be fully utilized
Solution Approach 1:
The patent implements a coordination mechanism where the memory access unit receives and manages memory access requests from multiple AFUs. This centralized management provides feedback control over task distribution, ensuring balanced workload allocation across AFUs and maximizing overall system performance while maintaining task sharing capability.
Data Source
AI summary
A processing system includes at least one core, at least one accelerator function unit (AFU), a microcontroller, and a memory access unit. The AFU and the core share a plurality of virtual addresses to access a memory. The microcontroller is coupled between the core and the AFU. The core develops and stores a task in one of the virtual addresses. The microcontroller analyzes the task and dispatches the task to the AFU. The AFU accesses the virtual address indicating where the task is stored through the memory access unit to executes the task.