Microcontroller Memory Power Reduction via Standby Interface
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Solution Overview
Problem
Existing power management techniques for micro-controllers in low-power modes, such as SLOW mode, do not effectively reduce memory power consumption, as memory remains active and consumes power even when not accessed.
Innovation Solution
A memory interface that manages a STAND-BY low-power mode, using an asynchronous read access protocol and a dedicated analog circuit to monitor the 'Ready' signal, ensuring the memory is only powered for the duration of read/write operations, and returns to STAND-BY mode thereafter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the micro-controller is working in SLOW mode with low-frequency oscillator, then power consumption is reduced, but memory remains active and continues to consume power
Solution Approach 1:
The memory interface dynamically adjusts memory operation modes based on system state. When the micro-controller is in SLOW mode, the interface puts the memory in STAND-BY mode to reduce power consumption. When memory access is required, the interface transitions the memory to active mode. This dynamic adaptation resolves the contradiction by making memory power consumption variable rather than constant.
Solution Approach 2:
The system changes the operational parameters of the memory by transitioning between STAND-BY mode and active mode. The memory interface monitors system conditions and adjusts memory power state accordingly, changing the power consumption parameter from continuous to intermittent, thereby reducing overall energy loss while maintaining functionality when needed.
2Speed
If the memory is kept active to ensure fast access, then access time is reduced, but power consumption increases
Solution Approach 1:
Instead of keeping the memory continuously active, the system employs periodic activation. The memory is activated only during periods when access is actually needed (when the micro-controller requires data from memory), and returned to STAND-BY mode otherwise. This periodic action pattern reduces power consumption while maintaining access speed when required, as the memory can be quickly woken from standby state.
3Use of energy by moving object
If the micro-controller enters low-power modes to save energy, then overall power consumption is reduced, but wake-up time increases
Solution Approach 1:
The memory interface performs preliminary preparation by keeping the memory in a quick-wake STAND-BY mode rather than fully powered down. This preliminary state allows the memory to be rapidly activated when the micro-controller wakes from low-power mode, reducing the overall wake-up time penalty. The memory is pre-positioned in a low-power but quickly activatable state, balancing energy savings with wake-up speed.
Data Source
AI summary
A system for reducing power consumption in processing apparatus including a memory comprises a clock controller for controlling the clock period of the processing apparatus to switch the processing apparatus to a slow operating mode wherein the clock period is longer then the time required to recover from memory standby mode plus the time to execute a read command in the memory. A memory management module is provided configured for controlling the status of the memory during the slow operating mode by:maintaining the in a stand-by mode when no memory read/write commands are to be executed, andif any said read/write commands are required to be executed, switching said memory on only for the time required to perform the memory read/write commands.