Microcontroller Internal Memory Segmentation for Speed
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Solution Overview
Problem
The existing microcontroller architecture requires multiple read operations from external memory for instruction execution, leading to inefficiencies due to the use of a single data bus for both read and write operations, which limits processing speed.
Innovation Solution
The proposed solution involves a central processing unit with an internal memory unit where instructions are stored in dedicated data areas, allowing direct reading and execution without the need for external memory access, and a dual-bus system for simultaneous read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If instructions are stored in external memory and accessed via a single data bus, then device complexity is reduced, but processing speed deteriorates due to multiple sequential read operations
Solution Approach 1:
The memory system is segmented into external memory for program storage and internal memory for instruction caching. The internal memory unit contains data areas that store instruction information parts, allowing the control circuit to directly read instructions without sequential external memory access, thereby resolving the speed-complexity contradiction.
Solution Approach 2:
Instruction information parts are preliminarily loaded into the internal memory unit before execution. The program data is stored in the internal memory such that instruction information parts are positioned in data areas, enabling the control circuit to immediately access and execute instructions without waiting for external memory read operations.
2Productivity
If a single data bus is used for both read and write operations, then device complexity is reduced, but productivity deteriorates due to inability to perform simultaneous read and write operations
Solution Approach 1:
The single data bus is segmented into a read data bus and a write data bus. This allows the control circuit to simultaneously perform read operations via the read data bus and write operations via the write data bus, eliminating the bottleneck of sequential operations while maintaining manageable system complexity.
Solution Approach 2:
The bus system transitions from a single-dimensional shared bus to a multi-dimensional bus structure with separate read and write pathways. This dimensional expansion enables parallel operation channels, allowing simultaneous read and write operations without significant increase in overall system complexity.
Data Source
AI summary
A program data area 38 storing program data is provided in an internal memory unit that a control circuit 31 of a CPU 3 can directly red from. The program data is constituted by instructions each comprising an instruction information part and an operand (i.e., a complementary information part) for use in execution of this instruction information part. The program data area 38 comprises a plurality of 24-bit data areas each having an address indicative thereof. One instruction is stored in one data area such that the instruction information part resides at the beginning of the data area.