Microcontroller Firmware Updates for Non-Volatile Memory Control

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Solution Overview

Problem

Existing memory systems require complex and costly redesigns for changes in memory operations, as state machines necessitate tape-out or engineering change orders for each design change, slowing down development and increasing costs.

Innovation Solution

A programmable and reprogrammable microcontroller is used, comprising a Core Processor to coordinate voltage sequences and a Sense Processor to test memory cell conditions, allowing for firmware updates without hardware changes, enabling flexible and efficient memory operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If state machines are used for memory operation control, then memory operations can be performed, but any design change requires tape-out or engineering change orders, slowing development and increasing costs

Engineering Contradiction:
Improveflexibility of memory operation changesVSAvoidcomplexity of redesign process
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent replaces static state machine control with a dynamic microcontroller that can be reprogrammed via firmware updates. The microcontroller executes instructions from memory, allowing the control logic to be changed without hardware modifications. This dynamic approach enables flexible updates to memory operations through software while maintaining a fixed hardware architecture, directly resolving the contradiction between adaptability and redesign complexity.

Inventive Principle:
Principle #15Dynamics

2Productivity

If state machines are used for memory operation control, then memory operations can be performed, but development time increases due to required tape-out or engineering change orders

Engineering Contradiction:
Improvespeed of developmentVSAvoidtime for redesign processes
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The microcontroller-based control system allows development iterations to be implemented through firmware updates rather than hardware redesigns. This dynamic software-based control enables rapid prototyping and testing, significantly reducing the time required for development cycles while maintaining full control over memory operations.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements control logic as executable instructions stored in memory that can be copied and updated without changing the underlying hardware. This allows development teams to iterate on control algorithms and memory operation sequences by simply loading new firmware, eliminating the time-consuming tape-out and engineering change order processes associated with state machine redesigns.

Inventive Principle:
Principle #26Copying

3Adaptability or versatility

If state machines are used for memory operation control, then memory operations can be performed, but development costs increase due to required tape-out or engineering change orders

Engineering Contradiction:
Improveability to change memory operationsVSAvoidcost of hardware redesign
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

By implementing control logic in programmable microcontroller firmware rather than fixed state machine hardware, the system enables costly hardware redesigns to be replaced with inexpensive software updates. This dynamic approach maintains full adaptability for changing memory operations while eliminating the high costs associated with tape-out and engineering change orders, making the system both adaptable and cost-effective.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10908817B2Signal reduction in a microcontroller architecture for non-volatile memory
Publication Date: 2021.02.02 SANDISK TECHNOLOGIES LLC
  • US10908817B2 patent drawing
  • US10908817B2 patent drawing
  • US10908817B2 patent drawing

AI summary

An apparatus includes a first processor that generates first control signals to control a first circuit to perform memory operations on memory cells. A first number of first physical signal lines delivers the first control signals to a conversion circuit. A second number of second physical signal lines delivers converted control signals to the first circuit. The conversion circuit is coupled by the first number of first physical signal lines to the first processor and by the second number of second physical signal lines to the first circuit. The conversion circuit converts the first control signals to the converted control signals, and outputs the converted control signals to the first circuit. The first number of first physical signal lines is less than the second number of second physical signal lines to reduce the first number of first physical signal lines coupled between the first processor and the first circuit.