Microcontroller Secure Access via Peripheral Controller
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Solution Overview
Problem
Existing microcontroller systems lack robust security measures to prevent information leakage from secure domains to non-secure domains, particularly in scenarios where critical information like cryptographic keys is processed, and there is a need to ensure secure execution and data isolation between secure and non-secure code.
Innovation Solution
A microcontroller system architecture with a secure and non-secure CPU, a system bus, and a peripheral access controller (PAC) that configures CPUs to operate in secure and non-secure modes, allowing secure access to peripherals while preventing non-secure access, using non-secure shared memory for data exchange and communication between CPUs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single CPU is used to operate in both secure and non-secure modes, then device complexity is reduced, but security robustness deteriorates due to potential information leakage between domains
Solution Approach 1:
The system is segmented into two distinct CPU instances: a secure CPU for executing security-critical code and a non-secure CPU for general applications. This segmentation prevents information leakage between secure and non-secure domains by providing physical isolation through separate execution environments, while both CPUs share the same system bus and memory space for controlled communication.
2Reliability
If secure memory is used to store critical code, then security is improved, but access control complexity increases
Solution Approach 1:
A peripheral access controller (PAC) acts as an intermediary between CPUs and peripherals, managing access control policies. The PAC receives access requests from both secure and non-secure CPUs, evaluates them against configured security policies, and grants or denies access accordingly. This mediator approach simplifies the access control mechanism by centralizing security decisions in a dedicated controller rather than implementing complex access control logic within each CPU or memory module.
3Reliability
If split domain architecture is implemented with separate secure and non-secure domains, then security robustness is improved, but device complexity increases
Solution Approach 1:
Both secure and non-secure CPUs share common system resources including the system bus, memory space, and peripheral interfaces. This multi-functionality approach allows a single system architecture to support both secure and non-secure operations without requiring completely separate hardware paths for each domain, thereby reducing overall system complexity while maintaining security isolation through the secure CPU's restricted access to sensitive resources.
4Reliability
If peripheral access is restricted to secure CPU only, then security is improved, but functionality deteriorates due to limited peripheral access for non-secure applications
Solution Approach 1:
The peripheral access control system dynamically adjusts access permissions based on the operational context. The PAC can configure different access policies for different peripherals and different operational states, allowing the secure CPU to access critical peripherals while enabling controlled access for the non-secure CPU to non-critical peripherals. This dynamic configuration capability maintains security for essential resources while providing functional flexibility for application-specific peripherals.
Data Source
AI summary
Systems, methods and computer-readable mediums are disclosed for providing secure access in a microcontroller system. In some implementations, a microcontroller system comprises a system bus and a secure central processing unit (CPU) coupled to the system bus. The secure CPU is configured to provide secure access to the system bus. A non-secure CPU is also coupled to the system bus and is configured to provide non-secure access to the system bus. A non-secure memory is coupled to the system bus and is configured to allow the secure CPU and the non-secure CPU to exchange data and communicate with each other. A peripheral access controller (PAC) is coupled to the system bus and configured to enable secure access to a peripheral by the secure CPU while disabling non-secure access to the peripheral based upon a non-secure state of the non-secure CPU.