Microcontroller Power Gating for Deep Sleep Energy Reduction

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Solution Overview

Problem

Microcontrollers face challenges in achieving very low power consumption due to interactions with sensors and peripherals, which limit their time in low power modes and require advanced power management protocols to optimize energy efficiency.

Innovation Solution

A microcontroller system with a processing unit supporting near or sub-Vt circuits, independently power-controlled memory blocks, a power control system with power gates, and a DMA controller that gates clocks, allowing for separate power domains and deep-sleep modes to minimize power usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If power mode switching is used to reduce microcontroller power consumption, then power usage is reduced, but the time the microcontroller can remain in low power mode is limited by frequent interrupts from peripherals

Engineering Contradiction:

Improvepower consumptionVSAvoidtime in low power mode

Core Design Contradiction:

Use of energy by moving objectVSDuration of action of moving object

Solution Approach 1:

The patent segments the microcontroller system into distinct power domains, allowing different components (CPU, memory blocks, peripherals) to be independently powered or placed in low-power states. This enables the microcontroller to maintain deeper sleep modes longer by selectively powering down non-critical segments while keeping essential functions operational.

Inventive Principle:

Principle #1Segmentation

2Use of energy by moving object

If lower supply voltage is used to reduce power consumption, then power usage is reduced, but processing speed and performance deteriorate

Engineering Contradiction:

Improvepower consumptionVSAvoidprocessing speed

Core Design Contradiction:

Use of energy by moving objectVSSpeed

Solution Approach 1:

The patent implements dynamic voltage scaling where the supply voltage to different power domains can be adjusted based on operational requirements. During active processing, higher voltages provide faster performance; during idle or low-activity periods, voltages are reduced to minimize power consumption, creating a dynamic adaptation to workload demands.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters (voltage levels, clock frequencies) of different components based on their current state and requirements. This allows each power domain to operate at optimal parameters for its current workload, balancing power consumption against performance needs in real-time.

Inventive Principle:

Principle #35Parameter changes

3Adaptability or versatility

If more memory blocks and peripherals are added to increase functionality, then system capability is improved, but power consumption increases

Engineering Contradiction:

Improvesystem functionalityVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

By dividing memory blocks and peripherals into separate power domains with independent power control, the system can enable only the functional segments currently needed while keeping other segments powered down, thus maintaining high functionality when required while minimizing power consumption during partial operation.

Inventive Principle:

Principle #1Segmentation

4Loss of energy

If power gating is applied to memory blocks to reduce power consumption, then leakage power is reduced, but access time and system responsiveness may increase

Engineering Contradiction:

Improveleakage powerVSAvoidmemory access time

Core Design Contradiction:

Loss of energyVSLoss of time

Solution Approach 1:

The system uses wake-up interrupt controllers and power management protocols to predict and prepare for upcoming memory access requirements. Before actual access is needed, the system can pre-activate relevant power domains, ensuring that when memory access is required, the components are already powered and ready, thus minimizing the time penalty while still achieving power savings during extended idle periods.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11822364B2Very low power microcontroller system

Publication Date: 2023.11.21 AMBIQ MICRO INC

AI summary

A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.