Microcontroller Power Estimation for Dynamic Load Transients
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Solution Overview
Problem
Current power management techniques for microcontrollers and SoCs struggle to efficiently optimize energy consumption, especially in always-on/connected devices with varying power consumption profiles due to the activation of multiple IPs.
Innovation Solution
The implementation of a System Power Transient Management (SPTM) component within microcontrollers, which includes a Policy Manager, Dynamic Transient Control, Dynamic Voltage Control, and Dynamic Frequency Control, to dynamically identify expected load transients and determine power control data, such as power modes and loop parameters, to optimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional power management techniques are used for microcontrollers with multiple IPs, then device functionality is maintained, but energy consumption cannot be efficiently optimized due to varying power consumption profiles
Solution Approach 1:
The patent implements dynamic power management by continuously monitoring the activity states of multiple IP blocks and adjusting power control data in real-time. The system transitions from static power management to dynamic adaptation based on actual runtime conditions, allowing the microcontroller to optimize energy consumption according to varying operational profiles of different IP blocks.
Solution Approach 2:
The system changes power consumption parameters dynamically by generating different power control data based on the activity states of IP blocks. This includes adjusting voltage and frequency parameters for different power domains according to actual workload requirements, thereby optimizing energy efficiency while maintaining necessary functionality.
2Power
If voltage changes are implemented to manage power consumption, then power control is achieved, but system complexity and response time to load transients increase
Solution Approach 1:
The system performs preliminary power management actions by predicting load transients before they occur. The power management circuit monitors activity indicators from IP blocks and proactively adjusts power delivery parameters in anticipation of upcoming load changes, thereby reducing response time and avoiding voltage droop without requiring reactive voltage changes.
Solution Approach 2:
The patent introduces a power management circuit as an intermediary between the IP blocks and power supply. This intermediary component uses machine learning models to predict power requirements and smoothly modulate power delivery, preventing direct voltage fluctuations and reducing the need for rapid voltage changes while maintaining stable power control.
3Measurement precision
If machine learning models are trained with accurate power consumption data, then power estimation accuracy is improved, but training time and computational resources increase
Solution Approach 1:
The system uses partial training data strategically selected to capture the most important power consumption patterns. Rather than exhaustively training on all possible scenarios, the machine learning model is trained on representative samples from different operational states, achieving sufficient accuracy for power management decisions while significantly reducing training time and computational overhead.
Solution Approach 2:
The power management system performs self-training by utilizing actual runtime power consumption data from the microcontroller's own operation. The machine learning model continuously learns from real-world usage patterns generated by the device itself, improving accuracy over time without requiring external training resources or prolonged offline training periods.
Data Source
AI summary
A microcontroller includes a plurality of (Intellectual Property) IP blocks each configured to perform one or more functions; a hardware power estimator circuit for estimating power of the microcontroller, the hardware power estimator including a hardware artificial neural network including a plurality of interconnected nodes arranged in one or more stages, wherein each individual stage comprises: a first input layer including values indicating activities of the microcontroller and/or indicating active cells of the microcontroller; a second input layer including a weighted set of values; an output layer including values calculated for the individual node stage; and at least one intermediate layer situated between the input layer and the output layer, wherein each node of the at least one intermediate layer comprises a multiply and adder (MADD) circuit that is configured to calculate a value for the respective node using values received from the first and second input layers.