Microcontroller RTCS Hardware Scheduling for Power Savings

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Solution Overview

Problem

Conventional microcontrollers face inefficiencies in power management due to the need for software-based computation of time offsets to wake up from Sleep mode, leading to increased power consumption and reduced battery life, especially in battery-operated devices.

Innovation Solution

A microcontroller with a programmable Real Time Clock & Scheduler Unit (RTCS) that includes a comparator, arithmetic logic unit, delta time register, and event logic unit, allowing for hardware-based scheduling and interrupt generation, minimizing software computation and optimizing power usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If software-based computation of time offsets is used to schedule wake-up events, then the microcontroller can wake up at scheduled times, but power consumption increases and battery life decreases

Engineering Contradiction:
Improvescheduled wake-up timingVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The RTCS unit autonomously computes time offsets and generates wake-up events without requiring CPU intervention. The hardware scheduler independently manages the timing function, allowing the CPU to remain in sleep mode and consume minimal power while the RTCS handles scheduling tasks on its own.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent replaces software-based timing computation with a hardware-based RTCS unit. This substitution eliminates the need for software loops and CPU execution during sleep mode, replacing them with dedicated hardware circuitry that consumes significantly less power while maintaining accurate scheduled wake-up functionality.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Duration of action of moving object

If the CPU remains in Sleep mode to save power, then battery life extends, but software computation of time offsets increases wake-up time and power consumption

Engineering Contradiction:
Improvebattery lifeVSAvoidwake-up computation time
Core Design Contradiction:
Duration of action of moving objectVSLoss of time

Solution Approach 1:

The RTCS unit pre-computes time offsets and prepares wake-up events before the CPU needs to wake up. By performing timing calculations in advance using hardware circuitry during the sleep period, the system eliminates the need for time-consuming software computations at wake-up time, thus reducing both wake-up duration and associated power consumption.

Inventive Principle:
Principle #10Preliminary action

3Use of energy by moving object

If hardware-based scheduling is implemented, then power consumption decreases and battery life extends, but device complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidscheduler unit structure
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The RTCS unit is designed as a multi-functional hardware block that combines timer, comparator, event register, delta time register, and arithmetic logic unit into a single integrated scheduler. This universal scheduling component handles multiple timing functions and event types, reducing the need for separate dedicated circuits and minimizing overall device complexity while maintaining low power consumption.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP2761387B1Microcontroller with scheduling unit
Publication Date: 2019.09.04 MICROCHIP TECHNOLOGY INC
  • EP2761387B1 patent drawingFigure 1
  • EP2761387B1 patent drawingFigure 2
  • EP2761387B1 patent drawingFigure 3

AI summary

A microcontroller has a central processing unit (CPU), a plurality of peripherals, and a programmable scheduler unit with: - a timer being clocked by an independent clock signal; - a comparator coupled with a timer register of said timer and having an output generating an output signal; - an event register coupled with said comparator; - a delta time register; and - an arithmetic logic unit controlled by the output signal of the comparator and with first and second inputs and an output, wherein the first input is coupled with the timer register or the event register and the second input is coupled with the delta time register and the output is coupled with the event register.