Microcontroller Hardware Safety Circuit for Fast Fault Isolation
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Solution Overview
Problem
Existing microcontrollers rely on software-based diagnostic self-tests for functional safety, which consume valuable resources and have limited diagnostic coverage and increased Fault Detection Time Interval (FDTI), necessitating an improved hardware-based safety system.
Innovation Solution
A microcontroller with hardware-based safety mechanisms, including dual central processing circuits in lockstep, error correction codes, watchdog timers, and an error controller to autonomously manage fault signals, ensuring safe operation by isolating faulty components and transitioning to a safe state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-based diagnostic self-tests are used for functional safety, then the microcontroller can detect faults, but resource consumption increases and Fault Detection Time Interval increases
Solution Approach 1:
The patent replaces software-based diagnostic self-tests with hardware-based safety mechanisms. Specifically, it implements dual central processing circuits operating in lockstep with hardware comparators that continuously compare their outputs, and hardware error correction code circuitry that automatically detects and corrects memory errors. This hardware-based approach eliminates the need for software-based monitoring, thereby reducing CPU resource consumption and memory usage while providing continuous fault detection with lower latency.
2Reliability
If software-based diagnostic self-tests are used for functional safety, then the microcontroller can detect faults, but Fault Detection Time Interval increases
Solution Approach 1:
The patent implements continuous hardware-based monitoring through dual central processing circuits operating in lockstep, where both circuits execute the same instructions simultaneously and their outputs are continuously compared by hardware comparators. This continuous comparison occurs at every clock cycle without interruption, enabling immediate fault detection as soon as a discrepancy occurs. Additionally, the error correction code circuitry continuously monitors memory operations, providing uninterrupted safety coverage that reduces the Fault Detection Time Interval compared to periodic software-based checks.
3Productivity
If hardware-based safety mechanisms are implemented, then resource consumption is reduced and FDTI is reduced, but device complexity increases
Solution Approach 1:
The patent segments the safety functionality into distinct dedicated hardware modules: dual central processing circuits for execution, separate comparator circuits for output comparison, independent error correction code circuitry for memory protection, and dedicated watchdog timer circuits. This segmentation allows each component to be optimized for its specific function and enables parallel operation, improving overall efficiency while making the complex system more manageable through functional separation.
4Measurement precision
If dual central processing circuits operating in parallel are used, then fault detection capability is improved, but device complexity increases
Solution Approach 1:
The patent employs dual central processing circuits that are essentially identical copies operating in lockstep, both executing the same program instructions simultaneously. This copying approach provides inherent redundancy for fault detection without requiring complex differentiating logic between the circuits. The simplicity of having two identical processing units enhances fault detection capability through comparison while minimizing the complexity increase compared to using fundamentally different verification methods.
Data Source
AI summary
A microcontroller with a hardware-based safety system is disclosed. The microcontroller may include a bus, a memory control circuitry operatively coupled to the bus, a safety mechanism circuitry operatively coupled to the bus, one or more first peripheral devices operatively coupled to the bus, one or more second peripheral devices operatively coupled to the bus, a comparator to compare output signals from at least one of the memory control circuitry, the safety mechanism circuitry, the one or more first peripheral devices, and the one or more second peripheral devices, and to trigger a fault signal in response of detecting a difference in the output signals, and an error controller operatively coupled to the bus to receive the fault signal and to set the microcontroller to a safe state.