Microcontroller Test Interface Access Control via Reset State

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Solution Overview

Problem

There is a challenge in securing access to integrated circuits while allowing for debugging and testing, as interfaces like JTAG provide a path for unauthorized access, creating a conflict between security and testing capabilities.

Innovation Solution

Implementing a microcontroller with a test interface that initializes a disabled state during reset, executing reset programming to optionally establish a further disabled state, and enabling memory access only if the further disabled state is not set, thereby controlling access through the test interface during microcontroller operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If the test interface is enabled for debugging and testing, then access to memory for testing purposes is improved, but unauthorized access to memory contents becomes easier

Engineering Contradiction:

Improveaccess to memory for testingVSAvoidunauthorized access to memory

Core Design Contradiction:

Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by establishing an initial disabled state of the test interface during reset initiation operation, before the microcontroller begins normal operation. This preliminary disabling prevents unauthorized access during the critical boot-up phase, while still allowing legitimate testing during normal operation when the interface is subsequently enabled.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements dynamics by making the test interface state changeable - transitioning from an initial disabled state during reset to an enabled state during normal operation. This dynamic state adjustment allows the system to adapt between security mode (disabled) and testing mode (enabled) based on operational requirements.

Inventive Principle:

Principle #15Dynamics

2Object-affected harmful factors

If the test interface is disabled to prevent unauthorized access, then memory security is improved, but debugging and testing capability is reduced

Engineering Contradiction:

Improveunauthorized access to memoryVSAvoiddebugging and testing capability

Core Design Contradiction:

Object-affected harmful factorsVSEase of operation

Solution Approach 1:

The patent applies preliminary action by disabling the test interface during the reset initiation operation before normal operation begins. This ensures security during the critical boot-up phase when the microcontroller is most vulnerable, while allowing debugging and testing to proceed normally once the system is fully initialized and the interface is enabled.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements segmentation by dividing the operational timeline into distinct phases: reset initiation operation (where the interface is disabled for security) and normal operation (where the interface can be enabled for testing). This temporal segmentation allows the system to optimize for security during critical phases and for testing during safe phases.

Inventive Principle:

Principle #1Segmentation

3Ease of operation

If the test interface is enabled during normal operation, then debugging capability is improved, but vulnerability to unauthorized access increases

Engineering Contradiction:

Improvedebugging capabilityVSAvoidmemory access security

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The patent applies preliminary action by establishing the initial disabled state during reset initiation, before any normal operation occurs. This preliminary security measure ensures that even if the interface is enabled during normal operation for debugging, the system maintains security awareness through the persistent disabled state established during the critical boot-up phase.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS8176281B2Controlling access to an embedded memory of a microcontroller

Publication Date: 2012.05.08 SK HYNIX INC

AI summary

A microcontroller (30) includes a processor (32), an embedded memory (46) operatively coupled to the processor (32), and a microcontroller test interface (34) operatively connected to the processor (32) and the memory (36). The microcontroller (30) responds to a reset signal to perform a reset initiation that causes an initial disabled state of the test interface (34) to be set and execution of initiation code with the processor (32). This code execution optionally establishes a further disabled state. The microcontroller (30) provides an enabled state of the test interface for memory (46) access through the test interlace (34) during microcontroller (30) operation subsequent to the reset initiation unless the further disabled memory (46) access state is established by execution of the initiation code.