Microcontroller with Write Data Comparison Circuit for Reliability

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Solution Overview

Problem

Conventional microcontrollers with dual or multi-core CPUs execute the same processing simultaneously, limiting processing performance and failing to enhance reliability and safety in applications requiring high processing power, such as automotive powertrain control.

Innovation Solution

A microcontroller design where multiple CPUs execute different applications, with a memory map register and a write data comparison circuit that collates and compares write data, enhancing processing performance and reliability by detecting failures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If two CPUs execute the same processing at the completely same timing to detect failures, then reliability is improved, but processing performance deteriorates

Engineering Contradiction:
Improvefailure detection capabilityVSAvoidprocessing performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent divides CPU operations into two segments: safety-critical operations that are executed by both CPUs for comparison, and non-safety operations that can be executed by a single CPU. This segmentation allows the system to maintain high reliability for safety functions while achieving high processing performance for non-safety functions, resolving the contradiction between reliability and productivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different execution strategies to different types of operations: dual-execution with comparison for safety-critical operations and single-execution for non-safety operations. This local differentiation of quality allows the system to optimize reliability where needed while maintaining high overall processing performance.

Inventive Principle:
Principle #3Local quality

2Productivity

If a single CPU is used to execute applications, then processing performance is improved, but reliability deteriorates

Engineering Contradiction:
Improveprocessing performanceVSAvoidfailure detection capability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent dynamically adjusts the execution strategy based on the safety requirements of each operation. The safety determination unit dynamically identifies which operations require dual-execution for reliability, allowing the system to maintain high processing performance while ensuring reliability for critical functions through adaptive resource allocation.

Inventive Principle:
Principle #15Dynamics

3Productivity

If dual-core or multi-core microcontrollers are used to improve processing performance, then productivity is improved, but device complexity increases

Engineering Contradiction:
Improveprocessing performanceVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent makes the comparison circuit and safety determination unit universal components that can evaluate and manage safety for multiple different operations across the system. This multi-functionality allows the safety mechanism to be applied systematically without proportionally increasing complexity for each additional CPU or operation, enabling the system to scale while maintaining manageable complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8291188B2Microcontroller and electronic control unit
Publication Date: 2012.10.16 RENESAS ELECTRONICS CORP
  • US8291188B2 patent drawing
  • US8291188B2 patent drawing
  • US8291188B2 patent drawing

AI summary

A microcontroller in which respective CPUs execute different applications so as to improve processing performance, and the respective CPUs execute an application that requires safety and mutually compare the results thereof so as to enhance the reliability of write data is provided. The microcontroller has a plurality of processing systems made up of a first CPU, a second CPU, a first memory and a second memory, and for the instruction processing about specific processing set in advance, the write to peripheral modules which are not multiplexed is executed twice, and the write data of the first time and the second time are mutually collated.