Microcrystalline Silicon Gate Electrode Silicide Peeling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional layer-stacked wiring using microcrystalline silicon thin films and metal thin films for gate electrodes in polycrystalline silicon TFTs experiences excessive silicide formation reactions during high-temperature annealing processes, leading to peeling issues due to changes in crystal structure and volume, which degrades film quality and reliability.
Innovation Solution
The layer-stacked wiring is configured with microcrystalline silicon thin films where crystal grains are predominantly short in the film thickness direction, with deposition conditions optimized to prevent quality degradation, and heat treatment processes are controlled to suppress silicide formation reactions, ensuring the microcrystalline silicon thin film remains intact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature annealing is applied to form polycrystalline silicon TFTs, then the mobility and driving capability are improved, but excessive silicide formation occurs between the microcrystalline silicon thin film and metal thin film, causing peeling and reducing reliability
Solution Approach 1:
The patent applies parameter changes by controlling the deposition rate of the microcrystalline silicon thin film to be 13 nm/min or less, which optimizes the crystal grain structure to have fewer grains with length ≥60% of film thickness. This parameter control suppresses excessive silicide formation during subsequent high-temperature annealing processes while maintaining the gate electrode's low resistance and reliability characteristics.
2Productivity
If the deposition rate is increased to improve productivity, then the manufacturing efficiency is improved, but the quality of the microcrystalline silicon thin film degrades, leading to increased silicide formation and peeling
Solution Approach 1:
The patent establishes a critical parameter threshold by setting the deposition rate at 13 nm/min or less. This parameter optimization ensures that the microcrystalline silicon thin film develops an appropriate crystal grain structure with reduced excessive grains, thereby preventing silicide formation during annealing while maintaining acceptable productivity levels.
Solution Approach 2:
The patent applies preliminary anti-action by controlling the deposition conditions in advance to prevent the formation of excessive crystal grains that would later cause silicide formation. By optimizing the deposition rate before the annealing process, the patent preemptively suppresses the harmful silicide reaction that would otherwise occur during high-temperature processing.
3Reliability
If a layer-stacked wiring structure is used to achieve low resistance, then the electrical conductivity is improved, but the interface between microcrystalline silicon thin film and metal thin film becomes prone to peeling due to silicide formation
Solution Approach 1:
The patent resolves this contradiction by optimizing the deposition rate parameter to 13 nm/min or less, which controls the crystal grain structure of the microcrystalline silicon thin film. This parameter control suppresses excessive silicide formation at the interface between the microcrystalline silicon and metal layers, thereby maintaining both the low-resistance characteristic and the interface bonding strength.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively prevents peeling of the microcrystalline silicon thin film, maintains high film quality, and enhances the reliability and low-resistance characteristics of the gate electrode, allowing for the production of high-definition LCD devices with improved productivity and reduced costs.
Implementation Method 1
The microcrystalline silicon thin film 8 making up the lower layer 8 of the gate electrode 10 is formed so that its crystal grains each having a length of the thin film in a direction of a film thickness being 60% or more of a film thickness of the thin film amount to 15% or less of total number of crystal grains making up the thin film
Implementation Method 2
a metal thin film (upper layer) 9 made of a chromium thin film with a thickness of 200 nm formed on the microcrystalline silicon thin film 8
Implementation Method 3
an annealing process (activating process) to activate an impurity such as phosphorus, boron, or a like implanted in advance into the polycrystalline thin film and a hydrogenating process to terminate an orbit being in an unbonded state (dangling bond) existing in the polycrystalline thin film and at an interface between the polycrystalline thin film and gate insulating film by using hydrogen are required
Data Source
AI summary
A layer-stacked wiring made up of a microcrystalline silicon thin film and a metal thin film is provided which is capable of suppressing an excessive silicide formation reaction between the microcrystalline silicon thin film and metal thin film, thereby preventing peeling of the thin film. In a polycrystalline silicon TFT (Thin Film Transistor) using the layer-stacked wiring, the microcrystalline silicon thin film is so configured that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 60% or more of a film thickness of the microcrystalline silicon thin film amount to 15% or less of total number of crystal grains or that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 50% or less of a film thickness of the microcrystalline silicon thin film amount to 85% or more of the total number of crystal grains making up the microcrystalline silicon thin film.