Micro-Device Bonding with 3D Nanostructures at Low Temperature
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Solution Overview
Problem
Current bonding technologies for micro-devices face challenges in achieving reliable and efficient bonding, particularly with decreasing pixel pitch, where surface area and structural mismatch issues lead to reduced yield and reliability.
Innovation Solution
The use of 2D and 3D nanostructures on substrates, including nanotextured metal, nanoporous structures, and aligned nanowires, to increase bonding surface area and interlocking capabilities, combined with controlled temperature and pressure during the bonding process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bonding technologies are used for micro-devices, then the bonding process is simple, but the yield and reliability decrease due to surface area and structural mismatch issues
Solution Approach 1:
The patent transitions from conventional planar bonding to three-dimensional interlocking bonding structures. The receiver substrate includes protrusions that extend into cavities of the donor substrate, creating vertical interlocking features that significantly increase the effective bonding surface area and mechanical strength, thereby resolving the reliability issue while maintaining process feasibility
Solution Approach 2:
The bonding interface is segmented into multiple discrete interlocking features (protrusions and cavities) distributed across the bonding surface. This segmentation allows for localized bonding strength enhancement and provides tolerance for misalignment, improving overall bonding reliability without requiring complete surface contact
2Productivity
If pixel pitch is decreased to increase device density, then device integration is improved, but bonding reliability deteriorates due to reduced surface area
Solution Approach 1:
The invention compensates for reduced planar surface area in high-density pixel configurations by utilizing the vertical dimension. The interlocking protrusions and cavities extend perpendicular to the bonding interface, creating three-dimensional bonding features that maintain sufficient bonding strength even when pixel pitch is reduced and planar area is limited
Solution Approach 2:
The protrusions of one substrate nest into the cavities of the other substrate, creating a nested interlocking configuration. This nesting approach maximizes the use of available space within the reduced pixel pitch constraints while maintaining strong mechanical and electrical connections
3Reliability
If bonding surface area is increased using nanostructures, then electrical conductivity and thermal stability are enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent employs nanoporous metal structures on the bonding surfaces, which provide high surface area-to-volume ratios that enhance both electrical conductivity and thermal stability. The porous structure allows for improved interfacial contact and heat dissipation while maintaining compatibility with standard nanofabrication processes
Solution Approach 2:
The bonding interface utilizes composite structures combining metal nanoporous materials with interlocking geometric features. This composite approach integrates the electrical and thermal benefits of nanoporous metals with the mechanical strength of three-dimensional interlocking, achieving multiple performance goals through a unified manufacturing process
Data Source
AI summary
This disclosure is related to integrating optoelectronics microdevices into a system substrate for efficient and durable electrical bonding between two substrates at low temperature. 2D nanostructures and 3D scaffolds may create interlocking structures for improved bonding properties. Addition of nanoparticles into the structure creates high surface area for better conduction. Application of curing agents before or after alignment of micro devices and receiving substrates further assists with formation of strong bonds.