Microelectronic Assemblies Lithographic Via Formation
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Solution Overview
Problem
Conventional microelectronic assembly technologies face challenges in achieving high I/O density, power delivery, and signal speed due to limitations in manufacturing processes, particularly with laser drilling, which results in large via pad sizes and misalignment, hindering the integration of double-sided IC dies within package substrates.
Innovation Solution
The use of lithographic processes to form vias instead of laser drilling, allowing for improved layer-to-layer alignment, smaller pad sizes, and customized via shapes, enabling higher I/O densities and more efficient power delivery while reducing package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If laser drilling is used to form vias, then manufacturing process is simple, but via pad sizes become large and alignment precision deteriorates
Solution Approach 1:
The patent replaces the mechanical laser drilling process with a lithographic process to form vias. This substitution enables precise patterning of via pads with controlled dimensions and improved alignment accuracy between layers, directly resolving the contradiction between manufacturing simplicity and via pad size/alignment precision.
Solution Approach 2:
The patent changes the fundamental process parameters from laser drilling to lithography, enabling via pad sizes to be reduced from conventional large dimensions to precisely controlled small dimensions with improved alignment. This parameter change maintains manufacturing feasibility while dramatically improving via pad size and alignment precision.
2Ease of manufacture
If conventional substrates are used, then manufacturing is straightforward, but interconnect pitch is constrained
Solution Approach 1:
The patent replaces conventional substrate manufacturing with lithographic via formation, enabling interconnect pitch to be reduced beyond conventional limits. This substitution allows for higher density interconnect arrangements while maintaining manufacturing feasibility through precise lithographic patterning.
3Quantity of substance
If double-sided IC dies are integrated, then I/O density increases, but manufacturing complexity increases
Solution Approach 1:
The patent uses lithographic processes to pre-form precise via patterns and alignment features before die attachment. This preliminary action establishes accurate registration marks and via geometries that simplify the subsequent double-sided die integration process, enabling high I/O density while managing manufacturing complexity through advance preparation.
Data Source
AI summary
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; and a die embedded in the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts and the second conductive contacts are electrically coupled to conductive pathways in the package substrate.