Microelectronic Packages With Cavities For Stacked Chip Assembly
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Solution Overview
Problem
Current microelectronic packaging technologies face challenges in minimizing the size of packaged chips on circuit boards, as even chip-scale packages occupy more area than individual chips, and existing stacked packages are complex and costly.
Innovation Solution
A packaged microelectronic element design featuring a dielectric element with protruding pins, exposed chip and package contacts, and a second dielectric element with openings, allowing for wire bonds or conductive masses to connect bond pads to chip contacts, enabling a compact and efficient stacked package assembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If chip-scale packages are used to minimize package area, then the package occupies area equal to or slightly larger than the chip area, but the aggregate area of multiple packaged chips is still greater than or equal to the aggregate area of individual chips
Solution Approach 1:
The patent implements stacked packages where multiple chip units are vertically arranged one above another, with each unit containing a chip mounted on a unit substrate. The units are nested within a common package assembly, allowing multiple chips to occupy the footprint of a single chip on the circuit board, thereby dramatically reducing the aggregate package area.
Solution Approach 2:
The invention transitions from a planar arrangement of packages to a three-dimensional stacked configuration. By utilizing the vertical dimension (z-axis) to stack multiple chip units, the package assembly occupies minimal area on the circuit board while accommodating multiple chips, effectively solving the area constraint problem.
2Area of stationary object
If stacked packages are implemented to conserve space on circuit panels, then multiple chips are mounted one above another in a common package assembly, but the structure becomes complex and costly
Solution Approach 1:
The unit substrate serves multiple functions: it provides mechanical support for the chip, carries electrical traces for interconnection, and features exposed contacts that facilitate both wire bonding and direct stacking connections. This multi-functionality reduces the need for additional specialized components, simplifying the overall structure.
Solution Approach 2:
The package assembly is divided into modular unit substrates, each capable of independently mounting a chip. These standardized units can be stacked and interconnected through exposed contacts, creating a systematic approach that reduces complexity compared to monolithic package designs.
3Reliability
If traditional substrates with extensive traces and leads are used to connect chip contacts to package terminals, then electrical connections are established, but the package size increases beyond chip scale
Solution Approach 1:
The patent removes the traditional substrate layer that extends beyond the chip boundaries. Instead, the chip is mounted directly on a compact unit substrate with minimal trace routing, and electrical connections are established through exposed chip contacts that protrude from the unit substrate, eliminating the need for extensive lead frames or large substrate areas.
Solution Approach 2:
The unit substrate is designed as a thin, compact structure that provides necessary electrical interconnection without adding significant bulk or area. The exposed chip contacts serve as flexible connection points that can be wire-bonded or directly connected to adjacent units, maintaining reliability while minimizing package footprint.
Data Source
AI summary
Packaged microelectronic elements are provided which include a dielectric element, a cavity, a plurality of chip contacts and a plurality of package contacts, and microelectronic elements having a plurality of bond pads connected to the chip contacts.