Microelectronic Assembly with Fine-Patterned Circuit Structure
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Solution Overview
Problem
Multi-chip packages with silicon interposers are expensive and difficult to fabricate due to the need for semiconductor processing in clean rooms and result in a large form factor, constraining miniaturization in portable devices, where compact packaging of numerous chips with many interconnections is required.
Innovation Solution
A microelectronic assembly using a dielectric element with conductive bumps and traces, where the circuit structure is made of dielectric layers with conductive features, allowing for reduced thickness and cost-effective fabrication, and the encapsulant surrounds the bumps to provide mechanical reinforcement and protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon interposers are used to provide high speed interconnections between multiple microelectronic elements, then electrical connectivity and bandwidth are improved, but manufacturing cost and fabrication difficulty increase due to the need for semiconductor processing in clean rooms
Solution Approach 1:
The patent replaces expensive silicon interposers with organic substrate boards that can be manufactured using standard PCB fabrication processes. The organic substrate serves as a disposable, cost-effective alternative to silicon, eliminating the need for clean room semiconductor processing while providing the necessary electrical interconnection functions through printed circuit traces and solder ball arrays.
Solution Approach 2:
The patent substitutes the mechanical/semiconductor fabrication system with a chemical/electrical system. Instead of using semiconductor processing equipment to create conductive paths in silicon, the invention uses PCB manufacturing techniques involving copper traces, solder balls, and organic substrates to achieve the same electrical interconnection function.
2Strength
If silicon interposers with thick wafers are used to support multiple microelectronic elements, then structural support and electrical interconnection are provided, but the horizontal area and form factor increase, constraining miniaturization
Solution Approach 1:
The patent changes the physical parameters of the substrate by transitioning from thick silicon wafers to thin organic substrate boards. This parameter change reduces the horizontal area and form factor while maintaining the necessary structural support through the organic substrate's design, enabling miniaturization for portable devices.
Solution Approach 2:
The patent uses composite materials by combining organic substrate with copper traces, solder balls, and protective encapsulants. This composite structure provides the necessary structural support and electrical interconnection functions in a compact form factor, replacing the homogeneous thick silicon wafer structure.
3Reliability
If multiple levels of contacts and vias are drilled and plated to create electrical connections through the interposer, then electrical interconnection capability is improved, but manufacturing complexity and production time increase
Solution Approach 1:
The patent replaces the mechanical drilling and plating process with a PCB manufacturing process. Instead of drilling holes through thick silicon and electroplating conductive paths, the invention uses standard PCB techniques including copper foil lamination, screen printing of conductive paste, and reflow soldering to create electrical connections, significantly reducing production time.
Solution Approach 2:
The patent uses disposable organic substrate boards with pre-formed or easily created conductive paths, eliminating the need for time-consuming drilling and plating operations. The organic substrate can be manufactured with integrated conductive traces using standard PCB processes, reducing production steps and time.
4Length of stationary object
If the bulk of the silicon wafer is ground down or discarded to create the interposer structure, then the interposer thickness is reduced for better integration, but material waste and manufacturing cost increase
Solution Approach 1:
The patent uses disposable organic substrate boards that are manufactured to the required thickness from the beginning, eliminating the need to grind down thick silicon wafers. The organic substrate material is used efficiently without generating significant waste, as the substrate is manufactured in the desired form factor using PCB fabrication processes.
Data Source
AI summary
A microelectronic assembly includes a dielectric element having bumps projecting from a first surface thereof, the bumps having end surfaces flush with a planarized encapsulation. A circuit structure having a thickness less than or equal to 10 microns, formed by depositing two or more dielectric layers and conductive layers on the respective dielectric layers, has electrically conductive features thereon which electrically contact the bumps. The circuit structure can be formed separately on a carrier and then joined with the bumps on the dielectric element, or the circuit structure can be formed by a build up process on the planarized surface of the encapsulation and the planarized surfaces of the bumps.