Microelectronic Assembly With Mixed-Pitch Die Interconnects

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Solution Overview

Problem

Conventional substrates for integrated circuit dies face limitations in interconnect pitch due to manufacturing, materials, and thermal constraints, hindering efficient communication and power delivery between dies.

Innovation Solution

The use of die-to-package substrate (DTPS) and die-to-die (DTD) interconnects with mixed-pitch configurations, along with a package substrate that supports fine-pitch semiconductor dies, allows for reliable attachment and improved power delivery, signal speed, and design flexibility in microelectronic assemblies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional substrates are used for integrated circuit dies, then manufacturing and materials are simplified, but interconnect pitch is constrained and cannot achieve fine-pitch requirements

Engineering Contradiction:
Improveinterconnect pitchVSAvoidmanufacturing complexity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The system segments the interconnect structure into multiple layers: a first interconnect layer formed directly on the substrate, and a second interconnect layer formed on the first layer. This segmentation enables fine-pitch interconnects to be achieved in the first layer while the second layer provides broader routing capabilities, resolving the contradiction between pitch precision and manufacturing ease.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar interconnect routing to three-dimensional multi-layer routing. By adding vertical dimension with multiple interconnect layers, the system achieves fine-pitch connections without constraining the horizontal substrate layout, thereby improving interconnect pitch while maintaining manufacturing feasibility.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Temperature

If conventional substrates are used, then material selection is simplified, but thermal management becomes inadequate for high-density interconnects

Engineering Contradiction:
Improvethermal managementVSAvoidsubstrate structure
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The substrate is constructed as a composite structure with a first substrate layer and a second substrate layer, where each layer can be made from different materials optimized for specific functions. This composite approach enables superior thermal management capabilities while distributing structural complexity across multiple manageable layers.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The multi-layer substrate structure acts as an intermediary between the high-density interconnects and the external environment. The intermediate layers provide thermal pathways and heat dissipation routes, managing temperature effectively without requiring direct modification of the interconnect structures themselves.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If interconnect pitch is reduced for better communication, then bandwidth increases, but manufacturing precision requirements become more stringent

Engineering Contradiction:
Improvedata communication efficiencyVSAvoidinterconnect fabrication precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The interconnect system is segmented into specialized layers: the first interconnect layer is optimized for fine-pitch, high-bandwidth communication with correspondingly precise fabrication, while the second interconnect layer handles broader routing with relaxed precision requirements. This segmentation allows high data communication efficiency in critical paths without uniformly increasing manufacturing precision across the entire system.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250349820A1Microelectronic assemblies
Publication Date: 2025.11.13 INTEL CORP
  • US20250349820A1 patent drawing
  • US20250349820A1 patent drawing
  • US20250349820A1 patent drawing

AI summary

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.