Microelectronic Package With Edge Traces For Stacked Chip Interconnects
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Solution Overview
Problem
Existing microelectronic packaging technologies face limitations in stacking multiple chip packages due to the need for interconnecting elements to bridge gaps between packages, which restricts the number of connections that can be accommodated in a given size, especially when using overmolded packages with dielectric materials.
Innovation Solution
The development of a microelectronic package design that includes a package substrate with conductive elements and a dielectric mass forming an overmold with a top surface and edge surfaces, allowing for the exposure of top terminals and traces that extend along these surfaces, enabling closer proximity to the package substrate for increased connectivity without the need for extensive spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If interconnecting elements are spaced at relatively large intervals to bridge the gap between packages, then the gap between packages can be bridged, but the number of interconnecting elements that can be accommodated is limited
Solution Approach 1:
The patent transitions from planar connections to three-dimensional connections by forming conductive traces that extend along the vertical sidewalls of the dielectric mass. This allows interconnecting elements to be positioned at closer horizontal intervals while still bridging the vertical gap between packages, effectively utilizing the vertical dimension to increase connection density.
Solution Approach 2:
The dielectric mass is formed with predetermined vertical sidewalls that provide a structured pathway for conductive traces. This pre-formed structure cushions and guides the interconnecting elements, allowing them to be positioned at optimal intervals without requiring large spacing to bridge the gap between packages.
2Area of stationary object
If all interconnecting elements are accommodated in the limited region outside the overmold, then the package structure is compact, but the density of connections is reduced
Solution Approach 1:
The patent utilizes the vertical sidewall surface of the dielectric mass as an additional connection region. Conductive traces extend along these vertical surfaces, effectively transforming a two-dimensional connection plane into a three-dimensional connection volume, thereby increasing connection density without expanding the horizontal footprint.
Solution Approach 2:
The patent creates different functional zones on the dielectric mass surface: horizontal top surface for certain connections and vertical sidewalls for other connections. This local differentiation allows optimal positioning of interconnecting elements in different regions, maximizing the use of available space for connections.
3Adaptability or versatility
If the package substrate of the higher package sits above the dielectric overmold, then the packages can be stacked, but an appreciable gap is created requiring larger spacing between interconnecting elements
Solution Approach 1:
The vertical sidewalls of the dielectric mass serve as an intermediary structure that bridges the gap between the higher package substrate and the lower package terminals. Conductive traces positioned along these sidewalls provide a continuous conductive path that spans the vertical distance, eliminating the need for large horizontal spacing to accommodate the gap.
Data Source
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AI summary
A package for a microelectronic element 48, such as a semiconductor chip, has a dielectric mass 86 overlying the package substrate 56 and microelectronic element 48 and has top terminals 38 exposed at the top surface 94 of the dielectric mass 86. Traces 36a, 36b extending along edge surfaces 96, 108 of the dielectric mass 86 desirably connect the top terminals 38 to bottom terminals 64 on the package substrate 56. The dielectric mass 86 can be formed, for example, by molding or by application of a conformal layer 505.