Microelectronic Package With Nested Molded Body And Core RDL
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Solution Overview
Problem
Conventional microelectronic packaging methods, such as FO-WLP, lack sufficient mechanical protection for semiconductor die and core Redistribution Layers (RDL) within the package, and face challenges in achieving high product yields, especially when complex interconnection schemes are required.
Innovation Solution
A packaging method that integrates semiconductor die with core RDL layers surrounded by an encapsulant, allowing for additional mechanical protection and enabling testing before final packaging, which results in a compact package with enhanced structural integrity and high yields, even with complex interconnection schemes. This method includes forming core RDL layers over semiconductor die using RCP or CSP processes, followed by encapsulation and the addition of topside RDL layers for increased I/O pin count and protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If conventional FO-WLP packaging methods are used, then the package can be formed with basic structure, but mechanical protection for semiconductor die and core RDL is insufficient
Solution Approach 1:
The patent implements nested protection by placing the semiconductor die within an inner molded body, which is then enclosed by an outer molded body. The core RDL layers are positioned between these nested structures, providing mechanical protection at multiple hierarchical levels while maintaining structural organization.
Solution Approach 2:
The package structure is segmented into distinct functional regions: an inner molded body containing the semiconductor die, an outer molded body providing additional protection, and core RDL layers positioned between them. This segmentation allows each component to fulfill specific protective and interconnection functions independently.
2Quantity of substance
If complex interconnection schemes are implemented, then I/O pin count increases, but achieving high product yields becomes difficult
Solution Approach 1:
The core RDL layers are formed and positioned on the semiconductor die before the final packaging process. This preliminary formation of interconnection structures allows for early verification of interconnection integrity and enables selective assembly of known-good devices, thereby maintaining high product yields even with complex I/O configurations.
Solution Approach 2:
The core RDL layers serve as an intermediary structure between the semiconductor die and the external contact array. This intermediate layer enables complex interconnection schemes to be implemented while maintaining modularity and facilitating quality control at each stage of assembly.
3Productivity
If the package size is reduced to match die size, then manufacturing efficiency improves, but mechanical protection and I/O expansion are limited
Solution Approach 1:
The patent transitions from a two-dimensional planar package structure to a three-dimensional stacked configuration. The inner and outer molded bodies create vertical layers, allowing the package to provide enhanced mechanical protection and accommodate complex interconnections without significantly increasing the planar footprint, thus maintaining manufacturing efficiency.
Data Source
AI summary
Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method comprises encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body. The outer molded body has a portion, which circumscribes the core redistribution layer. One or more topside redistribution layers are produced over the core redistribution layer. A contact array is formed over the topside redistribution layer and electrically coupled to the first semiconductor die encapsulated in the outer molded body through the topside redistribution layers and the core redistribution layers.