Microelectronic Package Terminal Configuration for Stub Minimization

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Solution Overview

Problem

Conventional microelectronic packages have terminal configurations that lead to long signal stubs on circuit panels, causing electrical performance issues such as increased settling time, ringing, and intersymbol interference, particularly when carrying address and clock information.

Innovation Solution

The microelectronic package design includes terminals configured to carry address and command signals in a central region rather than peripheral edges, reducing stub lengths by aligning corresponding terminals in mirror image grids on opposite surfaces of the circuit panel, thereby minimizing electrical connections and improving signal integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If terminals are placed at peripheral edges of the package substrate, then the package can accommodate more I/O connections, but the stub length on the circuit panel increases causing electrical performance degradation

Engineering Contradiction:

Improvenumber of I/O connectionsVSAvoidelectrical performance degradation due to long stubs

Core Design Contradiction:

Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The patent inverts the conventional terminal placement approach by positioning terminals in a central region of the package substrate rather than at peripheral edges. This inversion allows the signal paths to be routed more efficiently, reducing stub lengths on the circuit panel while still accommodating the required number of I/O connections through strategic terminal arrangement in the central area.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent transitions from a two-dimensional peripheral arrangement of terminals to a three-dimensional configuration where terminals are distributed in a central region with vertical stacking and layered routing. This dimensional change enables shorter stub lengths by utilizing the vertical space and multiple routing layers within the package substrate, thereby improving electrical performance while maintaining high I/O capacity.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Object-affected harmful factors

If terminals are positioned to minimize stub lengths, then electrical performance improves, but the package area occupied increases

Engineering Contradiction:

Improveelectrical performanceVSAvoidpackage area

Core Design Contradiction:

Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

The patent merges multiple terminal functions and signal paths into a compact central region arrangement. By combining address terminals, command terminals, and data terminals in a centralized configuration with shared routing resources and vertical stacking, the design achieves short stub lengths for improved electrical performance while minimizing the overall package area footprint.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS10643977B2Microelectronic package having stub minimization using symmetrically-positioned duplicate sets of terminals for wirebond assemblies without windows

Publication Date: 2020.05.05 ADEIA SEMICON TECH LLC

AI summary

A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.