Microelectronic Packaging With Preformed Through Holes
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Solution Overview
Problem
Conventional microelectronic device packaging methods, such as die-level and wafer-level packaging, face challenges including high costs, damage to dies during handling, and difficulties in forming robust wire-bonds due to increased pin counts and smaller package sizes, as well as issues with laser drilling that require expensive alignment tools and increase production costs.
Innovation Solution
A method involving a substrate with preformed through holes arranged in arrays, where singulated microelectronic dies are attached with terminals aligned to the holes, and a redistribution structure is formed with conductive lines and contacts, allowing for efficient alignment and connection without damaging the dies, reducing the need for expensive alignment tools and desmearing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If die-level packaging is used to attach individual dies to interposer substrates, then robust wire-bonds can be formed, but the process is time consuming and expensive
Solution Approach 1:
The invention segments the packaging process by separating die attachment from wire-bonding. Dies are first attached to the substrate in an array, then wire-bonds are formed to connect multiple dies simultaneously to the interposer substrate, reducing overall processing time while maintaining robust connections
Solution Approach 2:
The invention merges multiple die attachment operations into a single process step by attaching arrays of dies simultaneously to the substrate. Similarly, wire-bonding operations are merged to connect multiple dies to the interposer substrate in one step, significantly improving productivity
2Area of stationary object
If wafer-level packaging is used to achieve high pin counts in small area, then packaging size is reduced, but the devices are not as robust as die-level packaged devices
Solution Approach 1:
The invention transitions from two-dimensional wafer-level packaging to a three-dimensional arrangement where dies are attached in arrays on vertical surfaces of the substrate. This dimensional change allows high pin counts in compact footprints while maintaining robust die-to-substrate connections similar to die-level packaging
3Manufacturing precision
If laser drilling is used to expose bond-pads through the dielectric layer, then conductive traces can be formed, but expensive alignment tools are required and production costs increase
Solution Approach 1:
The invention performs preliminary alignment by attaching dies to the substrate before forming conductive traces. The dies themselves serve as alignment references, eliminating the need for expensive laser alignment tools. Holes are then drilled through the dielectric layer to expose bond-pads that are already positioned relative to the substrate
Solution Approach 2:
The invention uses the die array pattern as a template or copy for hole placement. Instead of using expensive alignment tools to position each hole individually, the regular array pattern of dies provides a self-replicating reference that simplifies the hole drilling process and reduces equipment costs
4Ease of manufacture
If individual dies are handled and attached to interposer substrates, then packaging can be performed, but damage to bare dies may occur during handling processes
Solution Approach 1:
The invention merges multiple die attachment operations into a single process by attaching arrays of dies simultaneously to the substrate. This reduces the number of handling steps required, minimizing opportunities for die damage while maintaining packaging capability
Solution Approach 2:
The substrate serves as an intermediary that receives arrays of dies in a single attachment operation. This intermediary approach allows dies to be transferred from the wafer to the substrate in groups rather than individually, reducing handling complexity and potential for damage
Data Source
AI summary
Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. An embodiment of one such method includes forming a plurality of through holes in a substrate with the through holes arranged in arrays, and attaching a plurality of singulated microelectronic dies to the substrate with an active side of the individual dies facing toward the substrate and with a plurality of terminals on the active side of the individual dies aligned with corresponding holes in the substrate. The singulated dies are attached to the substrate after forming the holes in the substrate.