Microelectronic Pin Sharing for Boundary Scan Test

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Solution Overview

Problem

The existing microelectronic devices require a large number of dedicated pins for boundary scan testing, which increases fabrication costs and is redundant in other operation modes, as these pins are not functional outside the test mode.

Innovation Solution

A microelectronic device design that shares a pre-selected number of pins between the boundary scan test mode and normal function operation mode, utilizing a test signal route selector and a mode selection input pin to route test signals, allowing pins to function as data input, output, clock input, or system reset pins based on the mode selection signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dedicated pins are provided for boundary scan test interface, then test functionality is ensured, but the number of pins increases and fabrication cost rises

Engineering Contradiction:
Improvetest functionalityVSAvoidnumber of pins
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent applies multi-functionality by enabling pins to serve dual purposes: they function as normal I/O pins during operational modes and as boundary scan test pins during test mode. The TAP controller and mode selection mechanism allow the same physical pins to be dynamically reassigned for testing without requiring separate dedicated test pins, thereby reducing the total pin count while maintaining complete test functionality.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If dedicated pins are provided for boundary scan test interface, then test functionality is ensured, but fabrication cost increases

Engineering Contradiction:
Improvetest functionalityVSAvoidfabrication cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent reduces fabrication cost by making pins universal rather than dedicated. The same pins are used for both normal operation and boundary scan testing, eliminating the need to manufacture additional dedicated test pins. The control logic (TAP controller and mode selection) automatically manages the dual functionality, making the manufacturing process simpler and more cost-effective while ensuring complete test capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Quantity of substance

If pins are shared between test mode and normal operation mode, then pin count is reduced, but mode switching control is required

Engineering Contradiction:
Improvenumber of pinsVSAvoidmode switching control
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent introduces a TAP controller as an intermediary that mediates between the shared pins and the boundary scan test interface. This controller, along with mode selection logic, automatically manages the switching between normal operation mode and test mode based on external control signals. This intermediary mechanism simplifies the overall system by providing automatic mode management rather than requiring complex manual switching circuits.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Quantity of substance

If pins are shared between test mode and normal operation mode, then pin count is reduced, but pin assignment flexibility is required

Engineering Contradiction:
Improvenumber of pinsVSAvoidpin assignment flexibility
Core Design Contradiction:
Quantity of substanceVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic pin assignment where the function of each pin is not fixed but can change based on the operational mode. The TAP controller and mode selection logic dynamically reassign pin functions: during normal operation, pins serve their primary I/O functions, while during test mode, the same pins are dynamically reassigned to serve as boundary scan test pins (TDI, TDO, TCK, TMS, TRST). This dynamic reassignment provides the necessary adaptability without requiring additional pins.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7949919B2Microelectronic device and pin arrangement method thereof
Publication Date: 2011.05.24 REALTEK SEMICON CORP
  • US7949919B2 patent drawing
  • US7949919B2 patent drawing
  • US7949919B2 patent drawing

AI summary

The present invention provides a microelectronic device with a circuit core and a boundary scan test interface sharing a number of pre-selected pins. In the mode of a boundary scan test, the boundary scan test interface manipulates the input and output of the test signal through the shared pins. Pins necessary for the microelectronic device are therefore reduced.