Microelectronic Units with Segmented Vias and Compliant Interconnects
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Solution Overview
Problem
Conventional through-silicon vias (TSVs) in semiconductor chip packaging reduce available space for active circuitry, increase production costs, and pose reliability challenges due to stress distribution issues and mismatched thermal expansion coefficients between semiconductor chips and bonding structures.
Innovation Solution
The design of microelectronic units with conductive pads and vias, where the dielectric region has apertures that do not conform to the opening contours, allowing for compliant interconnects that can flex and reduce stress, and the use of conductive interconnects extending within these apertures for improved electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional through-silicon vias are used to connect bond pads with the second face, then electrical connection is achieved, but the portion of the first face available for active circuitry is reduced
Solution Approach 1:
The via structure is segmented into multiple parts: a first opening extending from the rear surface, and second openings extending from the first opening to the bond pads. This segmentation allows the via to connect through the substrate without requiring a single large through-hole, thereby preserving more area on the first face for active circuitry while maintaining electrical connectivity.
2Reliability
If conventional vias with thin dielectric insulation are used, then electrical connection is achieved, but stress distribution inside the vias becomes non-optimal
Solution Approach 1:
A dielectric material is provided within the first opening, extending from the rear surface toward the front surface but not reaching the bond pads. This dielectric material acts as a cushioning layer that distributes stress uniformly within the via structure, preventing stress concentration at the via walls and improving overall reliability of the electrical connection.
3Reliability
If the semiconductor chip is bonded to a polymeric substrate with higher CTE, then electrical connection is achieved, but the connections are under stress due to CTE mismatch
Solution Approach 1:
The dielectric material within the first opening has different thermal expansion properties compared to the surrounding structures. By carefully selecting the dielectric material parameters, the structure can accommodate CTE mismatch between the semiconductor chip and polymeric substrate, reducing thermal stress on the electrical connections during temperature cycling.
4Volume of moving object
If compact physical arrangements of chips are implemented, then device size is reduced, but interconnection complexity increases
Solution Approach 1:
The via structure utilizes the vertical dimension by creating openings that extend through the substrate thickness. This vertical routing approach allows compact planar arrangements of chips while maintaining simple interconnection paths, as connections are made directly through the substrate rather than requiring complex lateral routing on the chip surface.
Data Source
AI summary
A microelectronic unit, an interconnection substrate, and a method of fabricating a microelectronic unit are disclosed. A microelectronic unit can include a semiconductor element having a plurality of active semiconductor devices therein, the semiconductor element having a first opening extending from a rear surface partially through the semiconductor element towards a front surface and at least one second opening, and a dielectric region overlying a surface of the semiconductor element in the first opening. The microelectronic unit can include at least one conductive interconnect electrically connected to a respective conductive via and extending away therefrom within the aperture. In a particular embodiment, at least one conductive interconnect can extend within the first opening and at least one second opening, the conductive interconnect being electrically connected with a conductive pad having a top surface exposed at the front surface of the semiconductor element.