Two-Level Microelectronic Substrate for Interconnect Scaling
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Solution Overview
Problem
Existing microelectronic packaging solutions are costly due to the need for expensive high-density interconnect (HDI) substrates that implement restrictive design rules for the entire substrate area, despite only 20% of the area requiring these rules, leading to inefficiencies and high costs, especially in high-end server CPU and GPU packaging.
Innovation Solution
The solution involves breaking the space transformation into two levels: a first substrate using HDI PCB design rules for system-level interfaces and a second substrate with more restrictive design rules for die-level interfaces, reducing overall cost and enabling parallel die and substrate manufacturing, with pre-attachment of substrates before die attachment to minimize defects and reduce waste.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single HDI substrate is used to handle space transformation from die bump pitch to system board level pitch, then interconnect scaling is achieved, but substrate body size becomes very large and manufacturing cost increases
Solution Approach 1:
The patent divides the single HDI substrate into multiple smaller substrates arranged in a grid pattern. Each substrate handles a portion of the interconnect routing, with substrates coupled together through matching interconnect patterns. This segmentation allows the system to achieve the required space transformation without requiring a single large substrate body.
Solution Approach 2:
The patent implements a hierarchical interconnect structure where fine-pitch interconnects on individual substrates are nested within a coarser-pitch interconnect grid formed by the array of substrates. The microvia layers on each substrate provide fine-pitch routing, while the substrate array arrangement provides the overall pitch transformation to system board level, creating a nested multi-scale interconnect system.
2Manufacturing precision
If a single HDI substrate is used to handle space transformation, then interconnect scaling is achieved, but manufacturing cost increases due to expensive HDI substrates
Solution Approach 1:
By segmenting the interconnect function across multiple smaller substrates, the patent enables the use of less expensive manufacturing processes for each individual substrate. The fine-pitch HDI requirements are localized to specific regions on each substrate rather than requiring the entire substrate area to meet those specifications, reducing manufacturing cost.
Solution Approach 2:
The patent applies different design rules and manufacturing specifications to different regions of the substrate array. The areas requiring fine-pitch interconnects use HDI processes, while other areas can use standard PCB manufacturing. This local quality approach ensures that expensive HDI manufacturing is applied only where necessary rather than uniformly across the entire substrate system.
3Reliability
If substrates are attached before die attachment, then defect identification is improved and waste is reduced, but process complexity increases
Solution Approach 1:
The patent performs substrate assembly and testing before die attachment, allowing defects in the substrate interconnect structure to be identified and corrected prior to committing the die. This preliminary action includes forming the substrate array, creating interconnect patterns, and performing electrical tests on the substrate assembly independently of the die, enabling early defect detection without wasting expensive die.
Data Source
AI summary
A microelectronic package includes a first substrate (120) having a first surface area (125) and a second substrate (130) having a second surface area (135). The first substrate includes a first set of interconnects (126) having a first pitch (127) at a first surface (121) and a second set of interconnects (128) having a second pitch (129) at a second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes a third set of interconnects (236) having a third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with a microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.