Microelectronic Assemblies with Vertical Interconnects
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Solution Overview
Problem
Current microelectronic package structures face challenges in achieving compact, high-speed interconnections between complex chips with numerous input and output connections, as existing solutions do not adequately address the need for short, low-impedance interconnects that do not increase assembly size, particularly in portable devices and data servers.
Innovation Solution
A microelectronic assembly is designed with first and second support elements, where electrically conductive connectors project above the surfaces and are coupled, with encapsulation forming between the connectors to maintain height and prevent expansion, allowing for vertical interconnects with a desirable standoff height and tight packing, using conductive masses and solid metal posts for efficient electrical coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional interconnection structures are used between stacked chips, then electrical connections can be established, but the interconnect length increases and impedance increases, reducing signal speed and bandwidth
Solution Approach 1:
The patent transitions from horizontal interconnections to vertical interconnections by stacking chips vertically and using through-substrate vias to connect corresponding pads on different chip layers. This dimensional change reduces interconnect length and impedance, enabling high-speed signal propagation while maintaining compact footprint.
Solution Approach 2:
The patent implements nested stacking where multiple chips are vertically stacked and interconnected through the substrate, with each chip layer containing complete functional circuits. This nesting approach minimizes interconnect length by placing connected components in close vertical proximity, reducing signal propagation time and increasing bandwidth.
2Area of stationary object
If chip stacking is implemented to reduce footprint area, then assembly size decreases, but manufacturing complexity and alignment precision requirements increase
Solution Approach 1:
The patent divides the system into modular chip units that can be independently fabricated and then stacked. Each chip is a self-contained functional module with input/output pads that align with corresponding pads on adjacent chips through standardized via patterns, simplifying the overall stacking process despite the complex three-dimensional structure.
Solution Approach 2:
The patent pre-configures alignment features and via patterns on each chip before stacking. The substrate is prepared with predetermined via locations that guide the alignment of stacked chips, reducing the complexity of real-time alignment during assembly and enabling precise positioning without complex alignment mechanisms.
3Productivity
If through-substrate vias are used for vertical interconnection, then interconnect length is reduced and signal speed increases, but manufacturing precision requirements for via alignment increase
Solution Approach 1:
The patent employs self-aligning via structures where the via patterns on stacked chips automatically align through mechanical interlocking features or magnetic alignment elements integrated into the substrate and chip designs. This self-alignment mechanism reduces the need for high-precision external alignment equipment and maintains via alignment accuracy during the stacking process.
4Reliability
If conductive vias are formed through the substrate to connect stacked chips, then low-impedance interconnections are achieved, but the substrate manufacturing complexity and cost increase
Solution Approach 1:
The patent optimizes via parameters such as diameter, depth, and spacing to achieve low impedance while using standard substrate materials and manufacturing processes. By carefully selecting via dimensions and fill materials (such as copper or conductive epoxy), the patent achieves reliable electrical connections without requiring exotic materials or specialized manufacturing equipment, maintaining ease of manufacture.
Data Source
AI summary
A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. An encapsulation separates respective pairs of coupled first and second connectors from one another and may encapsulate the microelectronic element and fill spaces between the support elements. The first connectors, the second connectors or both may be partially encapsulated prior to electrically coupling respective pairs of first and second connectors in columns.