Multi-threaded Network Processor Microengine Packet Processing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional communication networks face limitations in packet processing speed as networks support increasing data transmission speeds, necessitating more efficient packet processing systems.

Innovation Solution

The use of multi-threaded network processors with microengines and a media and switch fabric (MSF) to break down and process network packets efficiently, allowing for parallel execution of threads and accurate packet reassembly and forwarding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional packet processing methods are used, then network devices can exchange data, but packet processing speed limits the exchange rate despite increasing physical transmission speeds

Engineering Contradiction:
Improvepacket processing speedVSAvoiddata exchange rate
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The packet processing system is divided into multiple independent microengines (e.g., 16 microengines in the network processor), each capable of independently processing packets. This segmentation allows parallel processing of multiple packets simultaneously, directly increasing packet processing speed and enabling the data exchange rate to keep pace with physical transmission speeds.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system transitions from single-threaded sequential processing to multi-threaded parallel processing by introducing multiple microengines that can execute different threads simultaneously. This dimensional change from one-dimensional sequential execution to multi-dimensional parallel execution dramatically increases processing throughput.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Speed

If multi-threaded microengines are used to increase processing speed, then packet processing becomes faster, but system complexity increases

Engineering Contradiction:
Improvepacket processing speedVSAvoidprocessor architecture complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

Each microengine is designed as a universal processing unit capable of executing multiple different thread types and handling various packet processing tasks. This multi-functionality reduces the need for specialized hardware for each task type, managing complexity while maintaining high processing speed through parallel execution.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system uses multiple identical copies of the microengine architecture rather than complex heterogeneous processors. Each microengine is a simplified copy that can handle multiple tasks, reducing individual unit complexity while achieving high overall processing speed through parallelism.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS7500239B2Packet processing system
Publication Date: 2009.03.03 BEIJING XIAOMI MOBILE SOFTWARE CO LTD
  • US7500239B2 patent drawing
  • US7500239B2 patent drawing
  • US7500239B2 patent drawing

AI summary

According to some embodiments, each of a plurality of threads receives a start signal from a previous thread and a data packet from a buffer. Each thread issues a command to store the data packet in a memory, receives a continue signal from the previous thread, transmits a continue signal to a next thread after the data packet is stored in the memory, disposes of the data packet, receives an indication that the buffer has received a new packet, receives a start signal from the previous thread, and transmits a start signal to a next thread.