Micro-LED Display Backplane Tapered Pad Openings for Pin Alignment

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The challenge in the field of display technologies is to improve the yield in fabricating micro-LED display panels, which is hindered by the difficulty in accurately positioning and soldering micro-LED pins onto the display backplane without displacement during the welding process.

Innovation Solution

A display backplane design featuring a planarization layer with via holes and a passivation layer having through holes, where the top opening is smaller than the bottom opening, allows LED pins to be confined and securely soldered to pads, preventing displacement during transfer and welding, and utilizing a flange around the pin body for additional stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional flat through holes are used for LED pin positioning, then the fabrication process is simple, but the LED pins easily displace during transfer and welding

Engineering Contradiction:
Improvepositioning accuracyVSAvoidthrough hole structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The through hole in the passivation layer is designed with an asymmetric tapered structure where the top opening area is smaller than the bottom opening area. This asymmetric geometry creates a mechanical constraint that prevents LED pins from displacing laterally during transfer and welding operations, while maintaining fabrication feasibility through standard etching processes.

Inventive Principle:
Principle #4Asymmetry

2Stability of the object's composition

If the top opening of through hole is made smaller to prevent pin displacement, then positioning stability improves, but manufacturing precision requirements increase

Engineering Contradiction:
Improvepin positioning stabilityVSAvoidthrough hole dimensional control
Core Design Contradiction:
Stability of the object's compositionVSManufacturing precision

Solution Approach 1:

The through hole dimensions are optimized with specific parameter ranges: top opening diameter of 3-5 μm and bottom opening diameter of 5-8 μm. This parameter configuration provides sufficient mechanical constraint for pin stability while remaining within the capabilities of standard semiconductor fabrication processes, balancing stability requirements with manufacturing precision.

Inventive Principle:
Principle #35Parameter changes

3Strength

If passivation layer thickness is increased to provide better coverage, then protection improves, but through hole fabrication difficulty increases

Engineering Contradiction:
Improvepassivation layer protectionVSAvoidthrough hole etching
Core Design Contradiction:
StrengthVSEase of manufacture

Solution Approach 1:

The passivation layer thickness is optimized to 3000-4000 angstroms, providing sufficient mechanical protection and electrical isolation for the underlying structures. This thickness range enables complete through-hole penetration using standard etching processes while maintaining adequate protective coverage, balancing protection requirements with fabrication ease.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12002913B2Display backplane and fabrication method thereof, display panel and fabrication method thereof
Publication Date: 2024.06.04 BOE TECHNOLOGY GROUP CO LTD
  • US12002913B2 patent drawing
  • US12002913B2 patent drawing
  • US12002913B2 patent drawing

AI summary

The present disclosure provides a display backplane including an array substrate including at least one pixel unit each including at least one TFT; a planarization layer covering the array substrate; a pad layer including pads on the planarization layer, surface of the pad away from the planarization layer being first surface, each pixel unit being provided with one pad electrically coupled to a driving thin film transistor in a corresponding pixel unit through via hole penetrating through the planarization layer; a passivation layer covering the pad layer and including through holes, each pad corresponding to one through hole, such that the first surface of each pad is exposed through corresponding through hole, and area of top opening of through hole is smaller than area of bottom opening thereof. The present disclosure further provides a fabrication method of the display backplane, a display panel and a fabrication method thereof.