Wafer-Level Micro-LED Bonding With Reduced Warpage and Alignment Demand
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Solution Overview
Problem
Current bonding methods for Micro-LED displays face challenges such as high alignment accuracy requirements, low bonding yield, and warpage due to thermal expansion coefficient differences, which hinder the achievement of high-resolution displays.
Innovation Solution
A method for preparing and bonding a wafer-level Micro-LED chip that involves metal patterning on the CMOS driving substrate, reducing the need for alignment and subsequent etching processes, and using wafer bonding with a reduced contact area to minimize warpage and improve bonding yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If traditional wafer-to-wafer bonding is used, then bonding strength is achieved, but significant warping occurs due to large contact area and thermal expansion coefficient differences
Solution Approach 1:
The patent divides the bonding interface into discrete bonding pads rather than using a continuous large-area contact. The bonding structure includes a bonding pad on the first substrate and a corresponding bonding electrode on the second substrate, creating localized bonding points that reduce overall warping while maintaining necessary bonding strength through concentrated contact areas.
2Manufacturing precision
If die-to-die bonding is used, then alignment accuracy is improved, but substrate removal becomes difficult and process complexity increases
Solution Approach 1:
The patent performs preliminary patterning of the bonding pad and bonding electrode structures before the bonding process. The bonding pad is formed on the first substrate with predetermined patterns, and the bonding electrode is prepared on the second substrate in advance. This preliminary action simplifies the subsequent bonding process and avoids the need for complex substrate removal operations.
3Ease of manufacture
If adhesive bonding is used, then process simplicity is achieved, but it is only applicable for devices with pixel spacing greater than 100 micrometers
Solution Approach 1:
The patent changes the bonding parameters by using a bonding pad structure with controlled dimensions and patterns. The bonding pad size, shape, and distribution are optimized to enable effective bonding at pixel spacings below 100 micrometers while maintaining process simplicity. This parameter optimization allows the method to achieve both fine-pitch compatibility and manufacturing ease.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces alignment accuracy requirements, enhances bonding yield, and minimizes warpage, effectively achieving high-resolution Micro-LED displays without compromising bonding strength and stability.
Implementation Method 1
the first photoresist layer and the CMOS driving substrate are processed by using a photolithography process to expose pixel areas on the CMOS driving substrate
Implementation Method 2
metal electrodes are patterned and grown on the pixel areas
Implementation Method 3
metal electrodes are patterned and grown on the pixel areas
Implementation Method 4
a silicon dioxide (SiO2) insulation layer is deposited on the metal electrodes and a part of the CMOS driving substrate not covered by the metal electrodes
Implementation Method 5
a positive photoresist is spin coated on the SiO2 insulation layer to form a second photoresist layer on the SiO2 insulation layer. A part of the SiO2 insulation layer on the metal electrodes is etched
Implementation Method 6
a Micro-LED chip is bonded with the first structure by using a bonding process
Implementation Method 7
a substrate of the Micro-LED chip after the bonding process is stripped off to expose a GaN layer of the Micro-LED chip
Implementation Method 8
a substrate of the Micro-LED chip after the bonding process is stripped off to expose a GaN layer of the Micro-LED chip
Implementation Method 9
the positive photoresist is spin coated on the GaN layer of the Micro-LED chip to form a third photoresist layer on the GaN layer of the Micro LED chip, after exposure, the GaN layer, an ITO layer and a metal layer are etched to prepare Micro-LED pixels
Implementation Method 10
splashed ITO and a splashed metal on side walls of the Micro-LED pixels are corroded
Implementation Method 11
an insulation layer is deposited on the Micro-LED pixels and a part of the SiO2 insulation layer not covered by the Micro-LED pixels by using a composition process
Data Source
AI summary
A method for preparing and bonding a wafer-level chip used in micro light emitting diode (Micro-LED) includes: exposing pixel areas on a complementary metal oxide semiconductor (CMOS) driving substrate; patterning and growing metal electrodes; depositing a silicon dioxide (SiO2) insulation layer; bonding a Micro-LED chip; striping a substrate of the Micro-LED chip; preparing Micro-LED pixels; corroding splashed ITO and a metal on side walls of the Micro-LED pixels; preparing a co-negative electrode in the Micro-LED pixels. The method adopts a wafer bonding, which eliminates needs for alignment during bonding and compensates for the accuracy issue of die-to-die alignment. Before bonding, a metallization and passivation layer protection are applied to the CMOS surface to reduce chemical damage to the pixels and the CMOS. Compared to wafer-to-wafer, it reduces the bonding contact surface area, reduces stress during bonding, and improves bonding yield.