Micro-LED Chip Bonding Structure for High-Yield Mass Transfer
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Solution Overview
Problem
Micro-LED display technologies face challenges such as mass transfer difficulties due to the poor mechanical strength of AlGaInP materials, leading to reduced efficiency and increased product yield issues as chip size decreases.
Innovation Solution
A chip structure comprising a chip wafer unit with sub-pixel light-emitting layers and a color conversion layer unit, connected by an attaching layer such as an indium zinc oxide bonding layer, metal bonding layer, or adhesive glue layer, which improves transfer efficiency, reduces chip thickness, and enhances manufacturing precision and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If AlGaInP materials are used for Micro-LED, then high brightness and high luminescence efficiency are achieved, but mass transfer becomes difficult due to poor mechanical strength
Solution Approach 1:
The patent divides the Micro-LED chip into multiple independent chip wafer units, each with its own attaching layer. This segmentation allows each unit to be handled and transferred separately, improving mass transfer efficiency while maintaining the high brightness characteristics of AlGaInP materials.
Solution Approach 2:
The patent introduces an attaching layer as an intermediary between the chip wafer unit and the color conversion layer unit. This intermediary layer provides mechanical support and improves the overall mechanical strength of the structure, enabling easier mass transfer while preserving the optical properties of the AlGaInP Micro-LEDs.
2Measurement precision
If chip size is decreased, then display resolution is improved, but product yield decreases due to increased manufacturing difficulty
Solution Approach 1:
The patent performs preliminary actions by forming the attaching layer on the chip wafer unit before transferring it to the color conversion layer unit. This preliminary bonding ensures proper alignment and positioning, which is critical for maintaining high display resolution with smaller chip sizes while improving manufacturing yield through standardized transfer processes.
Solution Approach 2:
The patent replaces traditional mechanical transfer methods with a bonding-based approach using the attaching layer. This substitution eliminates the need for complex mechanical handling of tiny chips, thereby improving product yield while enabling the use of smaller chip sizes for higher resolution displays.
3Reliability
If attaching layer dimension is increased, then bonding stability is improved, but light emission is affected due to larger coverage area
Solution Approach 1:
The patent applies local quality by making the attaching layer's dimensional characteristics position-dependent. The attaching layer has a first dimension (l1) optimized for bonding stability and a second dimension (l2) optimized for light emission, with l1 ≥ l2. This local optimization ensures that the attaching layer provides sufficient bonding area while minimizing its impact on light emission area.
Solution Approach 2:
The patent changes the geometric parameters of the attaching layer, specifically controlling the ratio between its first dimension (l1) and second dimension (l2). By setting l1 ≥ l2, the patent achieves optimal bonding stability while minimizing the blocking effect on light emission, thus resolving the contradiction between bonding reliability and illumination intensity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed chip structure improves Micro-LED transfer efficiency, reduces chip thickness, and increases product yield by using attaching layers that provide stable bonding and precise alignment without affecting light emission.
Implementation Method 1
the first indium zinc oxide layer is connected with the second indium zinc oxide layer through a bonding interaction of molecular bonds
Implementation Method 2
the second metal sub-layer is an eutectic alloy layer connecting the first metal sub-layer and the third metal sub-layer
Data Source
AI summary
A chip structure is provided. The chip structure includes: a chip wafer unit and a color conversion layer unit arranged on a light-exit side of the chip wafer unit. The chip wafer unit includes a plurality of sub-pixel light-emitting function layers. The color conversion layer unit includes color conversion layers arranged on the light-exit side of the chip wafer unit. The chip structure further includes: an attaching layer, arranged between the chip wafer unit and the color conversion layer unit and configured to attach the chip wafer unit and the color conversion layer unit.