Micro-LED Chip Layout With Continuous Emitting Layer Isolation
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Solution Overview
Problem
Current micro-LED structures face challenges in optimizing the alignment and extension of conductive layers and light emitting layers to enhance efficiency and reliability, particularly in micro-LED chips with multiple LEDs where isolation and spacer configurations are critical for performance.
Innovation Solution
The micro-LED structure incorporates a first and second conductive layer with a light emitting layer in between, where the light emitting layer extends horizontally away from the edges of the conductive layers without contacting them, and includes spacers and isolation structures to improve carrier injection efficiency and optical performance, with specific configurations for alignment and placement to enhance micro-LED chip performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the light emitting layer contacts the conductive layers directly, then the device structure is simpler, but carrier injection efficiency deteriorates
Solution Approach 1:
An isolation layer is introduced between the light emitting layer and the conductive layers to prevent direct contact. This intermediary layer acts as a mediator that electrically isolates the n-type and p-type conductive layers while allowing the light emitting layer to maintain its light emission function, thereby improving carrier injection efficiency without significantly complicating the overall device structure.
2Illumination intensity
If the conductive layers extend beyond the light emitting layer edges, then electrical connection is improved, but optical performance deteriorates due to light leakage
Solution Approach 1:
The isolation layer extends to cover the edges of the light emitting layer, acting as an intermediary barrier that prevents light from leaking into the conductive layers. This maintains optimal optical performance while allowing the conductive layers to extend beyond the light emitting layer edges for improved electrical connection and carrier injection.
Solution Approach 2:
A thin film isolation layer is used to provide electrical and optical isolation without adding significant thickness to the device structure. This thin film effectively blocks light leakage while maintaining compact device dimensions and allowing flexible configuration of the conductive layers.
3Reliability
If spacers are added to isolate adjacent micro-LEDs, then cross-talk between LEDs is reduced, but manufacturing complexity increases
Solution Approach 1:
The isolation layer serves dual functions: it electrically isolates the n-type and p-type conductive layers from each other, and simultaneously acts as a spacer to isolate adjacent micro-LEDs on the same chip. By merging these two isolation functions into a single layer, the patent reduces manufacturing complexity while achieving both electrical isolation and optical isolation between adjacent LEDs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the efficiency and reliability of micro-LEDs by optimizing carrier injection and light emission, improving the performance and reliability of micro-LED chips, especially in multi-LED configurations by ensuring proper alignment and isolation between adjacent LEDs.
Implementation Method 1
a light emitting layer formed between the first type conductive layer and the second type conductive layer
Data Source
AI summary
A micro-LED chip includes multiple micro-LEDs. At least one micro-LED of the multiple micro-LEDs includes: a first type conductive layer; a second type conductive layer stacked on the first type conductive layer; and a light emitting layer formed between the first type conductive layer and the second type conductive layer. The light emitting layer is continuously formed on the whole micro-LED chip, the multiple micro-LEDs sharing the light emitting layer. A profile of the second type conductive layer perpendicularly projected on a top surface of the first type conductive layer is surrounded by an edge of the first type conductive layer.