MicroLED Optical Interconnects for High-Density Chip-to-Chip Links
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Solution Overview
Problem
Current electrical chip-to-chip interconnects face limitations in density and power efficiency due to fundamental constraints related to conductor width, layer count, and dielectric properties, which hinder the performance of advanced packaging technologies like 2.5D and 3D systems.
Innovation Solution
The implementation of 3D optical interconnects using microLEDs and photodetectors, which are integrated into optical transceiver ICs and coupled with optical propagation media such as multicore fibers, enabling high-density connections with reduced power consumption and increased reach.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electrical interconnects are used for chip-to-chip connections, then system performance is maintained, but interconnect density is limited and power consumption increases
Solution Approach 1:
The patent replaces electrical interconnects with optical interconnects using microLEDs as light sources. This substitution transitions from electrical signal transmission through conductors to optical signal transmission through waveguides, enabling higher density connections without the fundamental limitations of electrical interconnects such as capacitance and resistance
Solution Approach 2:
The patent changes the fundamental transmission medium from electrical to optical, utilizing light instead of electrical currents. This parameter change enables interconnect densities exceeding 2500 connections per mm² at 4 Gbps data rates, significantly surpassing traditional electrical interconnect capabilities
2Ease of operation
If electrical interconnects are used for chip-to-chip connections, then connections are established, but power consumption increases and reach is limited
Solution Approach 1:
The patent substitutes electrical signal transmission with optical signal transmission using microLEDs. Optical interconnects consume less power and provide extended reach compared to electrical interconnects, which are fundamentally limited by capacitance and conductor resistance
Solution Approach 2:
The patent implements 3D optical interconnects that extend connections in the vertical dimension through stacked chip architectures. This enables increased reach and connectivity options while maintaining low power consumption, as optical signals can traverse longer distances without significant signal degradation
3Quantity of substance
If conductor width and layer count are increased to improve interconnect density, then more connections are possible, but fundamental limitations based on dielectric permittivity and conductor resistance remain
Solution Approach 1:
The patent replaces the conductor-based electrical interconnect system with an optical waveguide system. This substitution eliminates the fundamental limitations imposed by dielectric permittivity and conductor resistance, allowing interconnect density to scale without encountering the same physical constraints that limit electrical interconnects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves interconnect densities exceeding 2500 connections per mm² at 4 Gbps data rates, providing a throughput density of >1 Pbps/cm², significantly surpassing the limitations of traditional electrical interconnects and enabling high-performance computing and networking applications.
Implementation Method 1
each of the transmitter instances including transmitter circuitry in the optical transceiver IC and a microLED
Implementation Method 2
each of the receiver instances including receiver circuitry in the optical transceiver IC and a photodetector
Data Source
AI summary
For optical communications between semiconductor ICs, optical transceiver assembly subsystems may be integrated with a processor. The optical transceiver assembly subsystems may be monolithically integrated with processor ICs or they may be provided in separate optical transceiver ICs coupled to or attached to the processor ICs.


