III-V Micro-LED Pixel Trench Design for Low Resistance Vias
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Solution Overview
Problem
The fabrication of vertically stacked micro-LED devices, such as QPI® display devices, faces a trade-off between maximizing mesa area for brightness and minimizing trench critical dimensions for low resistance through-layer electrical connections, while also requiring cost-effective lithography toolsets for mass production.
Innovation Solution
Incorporating cutouts in the pixel mesas to create non-uniform trench regions, allowing for wider trench areas and larger critical dimensions for through-layer via connections, which reduces via electrical resistance and improves overlay accuracy, enabling cost-effective fabrication and enhanced optical and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If trench critical dimensions are minimized for low resistance through-layer electrical connections, then electrical conductivity is improved, but mesa area is reduced
Solution Approach 1:
The pixel structure implements non-uniform trench widths with different regions optimized for different functions: narrower trenches in light-emitting regions to maximize mesa area and broader trenches in non-emissive regions to facilitate low-resistance electrical connections. This local differentiation resolves the contradiction by allowing both small trench dimensions for conductivity and large mesa area for brightness to coexist in different spatial locations.
2Illumination intensity
If uniform trench widths are used to maximize mesa area, then brightness is improved, but through-layer via fabrication becomes more difficult
Solution Approach 1:
The invention introduces non-uniform trench widths where specific regions have expanded dimensions to accommodate via fabrication requirements. The broader trenches in non-emissive areas provide adequate clearance for via formation processes while the narrower trenches in emissive areas preserve maximum light-emitting surface area, thus resolving the contradiction between brightness and manufacturability.
Solution Approach 2:
The pixel structure is segmented into different functional zones with distinct trench characteristics: light-emitting zones with narrow trenches for maximum aperture and non-emissive zones with wide trenches for via access. This segmentation allows the structure to simultaneously optimize for both optical performance and electrical connection fabrication.
3Reliability
If larger through-layer vias are fabricated to reduce electrical resistance, then electrical conductivity is improved, but lithography cost increases
Solution Approach 1:
The non-uniform trench design strategically places wider trenches only in the minimal necessary regions for via formation, rather than across the entire pixel structure. This localized approach allows via fabrication with moderate lithography capabilities while preserving narrow trenches elsewhere to minimize overall pixel area and reduce manufacturing costs.
Solution Approach 2:
The invention resolves the via size cost issue by transitioning from a uniform 2D trench pattern to a non-uniform 2D pattern with spatially varying dimensions. This dimensional variation in the trench width parameter enables adequate via access in specific zones without proportionally increasing the area and cost across the entire pixel array.
4Ease of manufacture
If non-uniform trench regions are introduced to enable wider via access, then via fabrication ease is improved, but pixel structure complexity increases
Solution Approach 1:
The non-uniform trench structure introduces complexity only where necessary for via fabrication in non-emissive regions, while maintaining simple narrow trench geometry in light-emitting regions. This localized complexity minimization ensures that the overall pixel structure remains relatively simple and manufacturable, resolving the contradiction between fabrication ease and structural complexity.
Data Source
AI summary
A III-V light emitting device with pixels (mesa regions) specifically designed to enable lower cost through layer vias is disclosed for reduced cost of manufacture of the device. Reduction of cost of manufacture is achieved by having non-uniform width trench regions formed during pixel etch for the multi-pixel array part of the device. Through-layer vias are specifically formed in the wider part of the trench regions using cheaper lithography toolset enabled by the larger via critical dimension achievable in the wider part of the trench regions (as compared to narrow part of the trench regions). Larger via critical dimension enables improved electrical (and consequently optical) performance of the device due to better overlay control as well as lower via resistance.