CMOS Micro-LED Power Plane Layout for Uniform Current Injection
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Solution Overview
Problem
Existing CMOS power plane layouts for microLED displays face challenges in uniform current distribution, leading to high current density and reliability issues due to non-uniform current distribution and excessive Ohmic losses, particularly in the μbumps, which compromise the performance and longevity of the LED devices.
Innovation Solution
A CMOS power plane layout with alternating Vled and Vcat contact areas and a large cathode redistribution ring is employed to uniformly distribute current along the four sides of the die area, using additional current distribution layers in parallel to reduce Ohmic losses and simplify the manufacturing process by minimizing the need for multiple μbump types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the number of metal layers for power planes is minimized, then manufacturing cost is reduced, but current distribution uniformity deteriorates leading to current crowding effects
Solution Approach 1:
The power plane structure is segmented into multiple functional zones: a first power plane layer providing primary current distribution, a second power plane layer providing additional current paths, and a third power plane layer completing the multi-layer current distribution network. This segmentation allows current to be distributed through multiple separate pathways rather than relying on a single complex layout, achieving uniform current distribution while maintaining manufacturing feasibility with standard multi-layer CMOS processes.
2Device complexity
If a simple power plane layout is used, then device complexity is reduced, but Ohmic losses increase due to non-uniform current distribution
Solution Approach 1:
The solution transitions from a two-dimensional single-layer power plane to a three-dimensional multi-layer power plane structure. By utilizing the vertical dimension with stacked power plane layers, the invention creates multiple current distribution pathways without increasing in-plane layout complexity. This dimensional expansion allows current to distribute more uniformly across the pixel array, reducing Ohmic losses while maintaining simple planar fabrication processes.
3Ease of manufacture
If current density in μbumps is not controlled, then manufacturing process is simplified, but reliability deteriorates due to excessive current density and heat losses
Solution Approach 1:
The multi-layer power plane structure acts as an intermediary between the pixel array and the μbumps, distributing current uniformly across multiple pathways before it reaches the interconnection points. This intermediary current distribution network prevents current crowding at the μbumps by providing alternative current paths through the multiple power plane layers, thereby protecting the interconnections from excessive current density and heat generation while maintaining a relatively simple manufacturing process.
Data Source
AI summary
Described is a CMOS power plane including interleaving contact areas, alternating Vled and Vcat contact areas, on at least two long sides of the μLED display area. By this way, Vled and cathode current are injected uniformly along the four sides of the μLED display panel. A large cathode current distribution ring on Vled and Vcat circuits is used to distribute the current along the four sides of the panel. The current distribution ring surrounds a pixel die area. An insulated area may be included on the cathode current redistribution ring adjacent one of the of μbumps.