Micro-LED Array Tunnel Junction Layout for Full-Color Uniformity
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Solution Overview
Problem
Existing methods for forming full-color micro-LED arrays, such as selective-area-growth (SAG) deposition, face challenges including non-uniform compositions, contamination from mask materials, and compromised p-type GaN surfaces, leading to reduced color purity and limited process windows.
Innovation Solution
A method involving the formation of first and second LED stacks on a substrate with a tunnel junction between n++ and p++ layers, allowing for geometry-independent deposition and selective removal without terminating on p-type semiconducting layers, thereby maintaining conductivity and avoiding mask-related contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If selective-area-growth (SAG) deposition is used to form full-color micro-LED arrays, then multiple LED colors can be integrated, but the growth conditions are severely influenced by local surroundings leading to non-uniform compositions and reduced color purity
Solution Approach 1:
The patent divides the LED array fabrication into separate growth stages: first growing all LED stacks uniformly across the substrate, then selectively removing portions to create the final pattern. This segmentation allows uniform growth conditions for all LEDs while achieving the desired geometric pattern, resolving the contradiction between full-color integration and composition uniformity.
Solution Approach 2:
Instead of the conventional approach of selectively growing LEDs only in desired areas (SAG), the patent inverts the process by growing LEDs uniformly across the entire substrate first, then selectively removing unwanted portions. This inversion eliminates the local surrounding influence during growth while still achieving precise geometric control in the final structure.
2Shape
If SAG deposition is used with mask materials, then patterned LED growth is achieved, but mask materials contaminate the active region with unwanted impurities
Solution Approach 1:
The patent extracts and eliminates the mask material from the process entirely. By growing LEDs uniformly across the substrate without masks and then selectively removing portions through etching, the method achieves patterned growth without introducing mask-related contamination to the active regions.
Solution Approach 2:
The patent introduces an intermediary etching process that replaces the direct mask-based patterning approach. The etching step acts as an intermediary mechanism to achieve geometric patterning without requiring mask materials to be in direct contact with the LED active regions, thereby preventing contamination.
3Manufacturing precision
If etching is terminated on p-type semiconducting Group III-nitride layers, then selective removal is achieved, but the conductivity of the p-type material is compromised
Solution Approach 1:
The patent applies local quality by creating different structural configurations in different regions of the substrate. In regions where LEDs are retained, the p-type layers maintain their full conductivity. In regions where LEDs are removed, the etching exposes underlying layers without compromising the p-type layers in retained regions, achieving selective removal precision while preserving local conductivity where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the formation of monolithic, full-color micro-LED arrays with improved color purity and process flexibility, as the method allows for independent growth and patterning of LED stacks across various geometries without compromising the conductivity of p-type layers.
Implementation Method 1
wherein a tunnel junction is formed at an interface between the n++ layer and the p++ layer
Implementation Method 2
the first LED stack comprises a plurality of first Group III-nitride layers defining a first semiconductor junction configured to output light having a first wavelength
Data Source
AI summary
A Light Emitting Diode (LED) array precursor is provided. The LED array precursor comprises a substrate having a substrate surface, a first LED stack, a p++ layer, a n++ layer and a second LED stack. The first LED stack is provided on a first portion of the substrate surface. The first LED stack comprises a plurality of first Group III-nitride layers defining a first semiconductor junction configured to output light having a first wavelength wherein a n-type side of the first semiconductor junction is orientated towards the substrate surface. The p++ layer is provided on the first LED stack, the p++ layer comprising a Group III-nitride. The n++ layer has a first portion covering the p++ layer of the first LED stack and a second portion covering a second portion of the substrate surface, wherein a tunnel junction is formed at an interface between the n++ layer and the p++ layer, the n++ layer comprising a Group III-nitride. The second LED stack is provided on the second portion of the n++ layer covering the second portion of the substrate surface. The second LED stack comprises a plurality of second Group III-nitride layers defining a second semiconductor junction configured to output light having a second wavelength different to the first wavelength, wherein a n-type side of the semiconductor junction is provided towards the n++ layer. A method of manufacturing a LED array precursor is also provided.